Woyu Zhang, Shaocong Wang, Yi Li, Xiaoxin Xu, Danian Dong, Nanjia Jiang, Fei Wang, Zeyu Guo, Renrui Fang, C. Dou, Kai Ni, Zhongrui Wang, Dashan Shang, Meilin Liu
{"title":"Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memory","authors":"Woyu Zhang, Shaocong Wang, Yi Li, Xiaoxin Xu, Danian Dong, Nanjia Jiang, Fei Wang, Zeyu Guo, Renrui Fang, C. Dou, Kai Ni, Zhongrui Wang, Dashan Shang, Meilin Liu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830418","DOIUrl":null,"url":null,"abstract":"Learning graph structured data from limited examples on-the-fly is a key challenge to smart edge devices. Here, we present the first chip-level demonstration of few-shot graph learning which homogeneously implements both the controller and associative memory of a memory-augmented graph neural network using a 1T1R resistive random-access memory (RRAM). Leveraging the in-memory computing paradigm, we validated the high end-to-end accuracy of 78% (GPU baseline 80%) and robustness on node classification of CORA dataset, while achieved 70-fold reduction in latency and 60-fold reduction in energy consumption compared with conventional digital systems.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830418","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Learning graph structured data from limited examples on-the-fly is a key challenge to smart edge devices. Here, we present the first chip-level demonstration of few-shot graph learning which homogeneously implements both the controller and associative memory of a memory-augmented graph neural network using a 1T1R resistive random-access memory (RRAM). Leveraging the in-memory computing paradigm, we validated the high end-to-end accuracy of 78% (GPU baseline 80%) and robustness on node classification of CORA dataset, while achieved 70-fold reduction in latency and 60-fold reduction in energy consumption compared with conventional digital systems.