{"title":"DC-to-5-GHz variable gain amplifier for high speed DSO","authors":"Yu-Lee Yen, C. Kuo, Ching-Feng Lee, Kevin Chen","doi":"10.1109/VLSI-DAT.2015.7114522","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a variable gain amplifier for the frontend circuitry of 5-GHz high-speed digital storage oscilloscopes. The design challenge includes wide bandwidth and low distortion over the frequency range from dc to 5 GHz. The Cherry-Hooper amplifier configuration is used to tackle the issue. The designed variable gain covers the specified range from -2 to 38 dB. The gain flatness carries out ripples less than 1 dB. To verify our approach, two versions of the amplifier circuits are fabricated. With four cascaded stages, the maximum gain achieves larger than 40 dB. The circuits are designed in 0.35 μm SiGe technology.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design, Automation and Test(VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2015.7114522","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents the design of a variable gain amplifier for the frontend circuitry of 5-GHz high-speed digital storage oscilloscopes. The design challenge includes wide bandwidth and low distortion over the frequency range from dc to 5 GHz. The Cherry-Hooper amplifier configuration is used to tackle the issue. The designed variable gain covers the specified range from -2 to 38 dB. The gain flatness carries out ripples less than 1 dB. To verify our approach, two versions of the amplifier circuits are fabricated. With four cascaded stages, the maximum gain achieves larger than 40 dB. The circuits are designed in 0.35 μm SiGe technology.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
