Linearity Improvement of the CMOS Power Amplifier with Auxiliary Path

Abstract

In this paper, a differential Cascode power amplifier has been presented. This P A includes two Cascode structure paths, main and auxiliary. This structure not only increases the drain efficiency but also improves linearity thanks to adopting auxiliary path. To achieve better linearity, two common source (CS) transistors have been biased in the different bias point (the main path CS transistor is biased in class-B, and the auxiliary path CS transistor is biased in class-AB). This work is analyzed and simulated in 0.18μm CMOS technology. The PAE and gain are achieved around 49.3% and 27.6dB for the input power of 6dBm, respectively while generating 30dBm output power. Also, the simulated ACPR for 16QAM with 6dB PAPR is −32dBc and −51dBc at offset frequency 5MHz and 10MHz, respectively.