A random access analog memory with master-slave structure for implementing hexadecimal logic

Abstract

A random access analog memory is designed without static power in this work. The analog memory appears the benefit on the great reduction of interconnections but suffers from the static power consumption and inaccuracy. As a hybrid, the hexadecimal signal processing is targeted in this paper. For storing hexadecimal values even implementing hexadecimal sequential logic, a master-slave structure is proposed with eighteen transistors, which is 28% of four pieces of binary master-slave flipflop. The hexadecimal voltage values are stored on the floating gate; and the read-out operations are executed by a comparator to protect the stored voltage. This comparator is powered only during the read-out operation. In this manner, the static power is eliminated. By using the proposed timing control mode, the master and slave stages are organized for hexadecimal sequential logic. As a demonstration, a sixteen-counter is designed on the basis of proposed analog memory without combinational logic circuits, in which the number of devices is reduced in contrast of binary approaches. From the circuit simulation results, the designed circuits maintain the hexadecimal values and execute hexadecimal functions correctly.