Using cap-integral standoffs to reduce chip hot-spot temperatures in electronic packages

Abstract

For high-power electronic packages, chip hot-spots and cross-chip temperature gradients represent a significant portion of the total thermal resistance from chip to ambient. This paper presents a technique of reducing the chip hot-spot temperatures using cap integral standoffs. The thermal benefit of the standoffs is shown experimentally and validated using thermal modeling. Thermal modeling is then extended to non-uniform power dissipation chips. Results show that the chip hot-spot temperature can be reduced by 5-10 /spl deg/C in a 100 W electronic package.