Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012464
M. Saini, R. Webb
Plane fin heat sinks, on which a small fan is mounted, are typically used for cooling the CPU in computers. The two most common air-flow configurations are parallel (or duct) flow and impinging flow. A number of analytic, numerical, and semi-empirical models have been published to predict heat sink performance. Most models assume uniform airflow (duct or impinging) at the heat sink inlet. The present work reviews some of the recent and representative models for the two flow configurations. A simple model based on developing laminar flow in rectangular channels is proposed. Experiments were conducted to measure hydraulic and thermal performance of two representative plane fin aluminum heat sinks, one for each flow configuration. The test data are compared with the proposed model for parallel flow and a selected model for impinging flow. A comparison of the proposed duct flow model predictions shows good agreement with the pressure drop and heat transfer data. Similarly good validation of the impinging flow model is established.
{"title":"Validation of models for air cooled plane fin heat sinks used in computer cooling","authors":"M. Saini, R. Webb","doi":"10.1109/ITHERM.2002.1012464","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012464","url":null,"abstract":"Plane fin heat sinks, on which a small fan is mounted, are typically used for cooling the CPU in computers. The two most common air-flow configurations are parallel (or duct) flow and impinging flow. A number of analytic, numerical, and semi-empirical models have been published to predict heat sink performance. Most models assume uniform airflow (duct or impinging) at the heat sink inlet. The present work reviews some of the recent and representative models for the two flow configurations. A simple model based on developing laminar flow in rectangular channels is proposed. Experiments were conducted to measure hydraulic and thermal performance of two representative plane fin aluminum heat sinks, one for each flow configuration. The test data are compared with the proposed model for parallel flow and a selected model for impinging flow. A comparison of the proposed duct flow model predictions shows good agreement with the pressure drop and heat transfer data. Similarly good validation of the impinging flow model is established.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127255225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012519
R. Webb, J. Gwinn
A high performance thermal interface material has been developed that consists of a 25 /spl mu/m coating of low-melting-temperature alloy (LMTA) tinned on each side of a 50 /spl mu/m copper substrate. The alloy has a melting point below the maximum CPU operating temperature. Steady-state tests per ASTM D-5470 show 0.058 K-cm/sup 2//W at 138 kPa contact pressure. Contact pressures as small as 34 kPa are permissible. Thermal cycling tests (1000 cycles) show negligible performance degradation, if the temperature is cycled less than 12 K above the melting point. Thermal cycling 20 K above the melting point results in degradation due to formation of a low thermal conductivity intermetallic alloy at the LMTA-copper interface. Removal and replacement of the LMTA results in negligible increase in interface resistance. Manufacturing methods are discussed, and a concept for the application of LMTA to the CPU-heatsink interface is presented. The LMTA alloy offers performance competitive with the best thermal grease, without the "messy" disadvantages of thermal grease.
{"title":"Low melting point thermal interface material","authors":"R. Webb, J. Gwinn","doi":"10.1109/ITHERM.2002.1012519","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012519","url":null,"abstract":"A high performance thermal interface material has been developed that consists of a 25 /spl mu/m coating of low-melting-temperature alloy (LMTA) tinned on each side of a 50 /spl mu/m copper substrate. The alloy has a melting point below the maximum CPU operating temperature. Steady-state tests per ASTM D-5470 show 0.058 K-cm/sup 2//W at 138 kPa contact pressure. Contact pressures as small as 34 kPa are permissible. Thermal cycling tests (1000 cycles) show negligible performance degradation, if the temperature is cycled less than 12 K above the melting point. Thermal cycling 20 K above the melting point results in degradation due to formation of a low thermal conductivity intermetallic alloy at the LMTA-copper interface. Removal and replacement of the LMTA results in negligible increase in interface resistance. Manufacturing methods are discussed, and a concept for the application of LMTA to the CPU-heatsink interface is presented. The LMTA alloy offers performance competitive with the best thermal grease, without the \"messy\" disadvantages of thermal grease.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127472546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012522
William Joseph Michael Nepean Moizer, William David Kanata Jeakins, D. Braun
Flow Network Models were used to design an innovative cooling system for a telecoms shelf which uses the partial recirculation of air to increase air velocities over the circuit cards. The paper is divided into two parts. The first part of the paper outlines the design of the recirculation cooling system, an outline of the design objectives, and a description of the Flow Network Model used. The second part of the paper outlines the measurements of the flow within the shelf. Flow measurements were performed with an Airflow Test Chamber (obstruction type flow meter) to measure bulk flow from which average slot velocities were calculated. These results are compared with the original Flow Network Model simulation results. Comparison of the measured and modeled data shows that there is a very close agreement in bulk flow prediction except for the recirculation bulk flow rate, and that difference was due to a much higher than anticipated density of power cables routed across the recirculation duct.
{"title":"Design and verification of a partial recirculation cooling scheme for a telecoms shelf","authors":"William Joseph Michael Nepean Moizer, William David Kanata Jeakins, D. Braun","doi":"10.1109/ITHERM.2002.1012522","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012522","url":null,"abstract":"Flow Network Models were used to design an innovative cooling system for a telecoms shelf which uses the partial recirculation of air to increase air velocities over the circuit cards. The paper is divided into two parts. The first part of the paper outlines the design of the recirculation cooling system, an outline of the design objectives, and a description of the Flow Network Model used. The second part of the paper outlines the measurements of the flow within the shelf. Flow measurements were performed with an Airflow Test Chamber (obstruction type flow meter) to measure bulk flow from which average slot velocities were calculated. These results are compared with the original Flow Network Model simulation results. Comparison of the measured and modeled data shows that there is a very close agreement in bulk flow prediction except for the recirculation bulk flow rate, and that difference was due to a much higher than anticipated density of power cables routed across the recirculation duct.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115072362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012469
Raghav Mahalingam, Ari Glezer
This paper discusses the development of active air-cooled heat sinks using synthetic jet ejector arrays for high power dissipation electronics. The heat sinks typically consist of a plate fin heat sink augmented with a synthetic jet module such that each fin is straddled by a pair of synthetic jets thereby creating a jet ejector that entrains cool ambient air upstream of the heat sink and discharges it into the channels between the fins. The present work characterizes three configurations of active integrated heat sinks designed for around 100 W power dissipation levels with respect to power dissipation, thermal effectiveness and package weight and volume. The flexibility of adapting synthetic jets for different heat sink designs is demonstrated by changing the relative orientation of the entrained and discharged air flow for the different cooling module designs, indicating the potential for controlling and utilizing limited air flow in spatially constrained environments. The performance of the heat sinks is assessed using an Intel thermal die instrumented with thermocouples. Using air temperature and velocity measurements the thermal effectiveness of heat sinks is compared with an off-the-shelf heat-sink-fan combination as well as with a steady flow past the heat sink. The jets generate an airflow in the range of 3-5 CFM, resulting in /spl sim/25 Watts/CFM for each device with a thermal effectiveness as high as 60-70%.
{"title":"Air cooled heat sinks integrated with synthetic jets","authors":"Raghav Mahalingam, Ari Glezer","doi":"10.1109/ITHERM.2002.1012469","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012469","url":null,"abstract":"This paper discusses the development of active air-cooled heat sinks using synthetic jet ejector arrays for high power dissipation electronics. The heat sinks typically consist of a plate fin heat sink augmented with a synthetic jet module such that each fin is straddled by a pair of synthetic jets thereby creating a jet ejector that entrains cool ambient air upstream of the heat sink and discharges it into the channels between the fins. The present work characterizes three configurations of active integrated heat sinks designed for around 100 W power dissipation levels with respect to power dissipation, thermal effectiveness and package weight and volume. The flexibility of adapting synthetic jets for different heat sink designs is demonstrated by changing the relative orientation of the entrained and discharged air flow for the different cooling module designs, indicating the potential for controlling and utilizing limited air flow in spatially constrained environments. The performance of the heat sinks is assessed using an Intel thermal die instrumented with thermocouples. Using air temperature and velocity measurements the thermal effectiveness of heat sinks is compared with an off-the-shelf heat-sink-fan combination as well as with a steady flow past the heat sink. The jets generate an airflow in the range of 3-5 CFM, resulting in /spl sim/25 Watts/CFM for each device with a thermal effectiveness as high as 60-70%.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115548556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012490
Xiaojin Wei, Y. Joshi
With smaller inlet flow velocity, a micro-channel stack requires less pumping power to remove a certain amount of heat than a single-layered micro-channel, because it provides a larger heat transfer area. A simple thermal resistance network model was developed to evaluate the overall thermal performance of a stacked micro-channel heat sink. Based on this simple model, in this study, a single objective minimization of overall thermal resistance is carried out using genetic algorithms. The aspect ratio, fin thickness and the ratio of channel width to fin thickness are the variables to be optimized, subject to constraints of maximum pressure drop (4 bar) and maximum volumetric flow rate (1000 ml/min). During the optimization, the overall dimensions, number of layers and pumping power (product of pressure drop and flow rate) are fixed. The study indicates that reduction in thermal resistance can be achieved by optimizing the channel configuration. The effects of number of layers in the stack, pumping power per unit area, and the channel length are investigated.
{"title":"Optimization study of stacked micro-channel heat sinks for micro-electronic cooling","authors":"Xiaojin Wei, Y. Joshi","doi":"10.1109/ITHERM.2002.1012490","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012490","url":null,"abstract":"With smaller inlet flow velocity, a micro-channel stack requires less pumping power to remove a certain amount of heat than a single-layered micro-channel, because it provides a larger heat transfer area. A simple thermal resistance network model was developed to evaluate the overall thermal performance of a stacked micro-channel heat sink. Based on this simple model, in this study, a single objective minimization of overall thermal resistance is carried out using genetic algorithms. The aspect ratio, fin thickness and the ratio of channel width to fin thickness are the variables to be optimized, subject to constraints of maximum pressure drop (4 bar) and maximum volumetric flow rate (1000 ml/min). During the optimization, the overall dimensions, number of layers and pumping power (product of pressure drop and flow rate) are fixed. The study indicates that reduction in thermal resistance can be achieved by optimizing the channel configuration. The effects of number of layers in the stack, pumping power per unit area, and the channel length are investigated.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116076953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012447
D. Gwyer, C. Bailey, K. Pericleous, D. Philpott, P. Misselbrook
For sensitive optoelectronic components, traditional soldering techniques cannot be used because of their inherent sensitivity to thermal stresses. One such component is the Optoelectronic Butterfly Package which houses a laser diode chip aligned to a fibre-optic cable. Even sub-micron misalignment of the fibre optic and laser diode chip can significantly reduce the performance of the device. The high cost of each unit requires that the number of damaged components, via the laser soldering process, are kept to a minimum. Mathematical modelling is undertaken to better understand the laser soldering process and to optimize operational parameters such as solder paste volume, copper pad dimensions, laser solder times for each joint, laser intensity and absorption coefficient. Validation of the model against experimental data will be completed, and will lead to an optimization of the assembly process, through an iterative modelling cycle. This will ultimately reduce costs, improve the process development time and increase consistency in the laser soldering process.
{"title":"Mathematical modelling: a laser soldering process for an optoelectronics butterfly package","authors":"D. Gwyer, C. Bailey, K. Pericleous, D. Philpott, P. Misselbrook","doi":"10.1109/ITHERM.2002.1012447","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012447","url":null,"abstract":"For sensitive optoelectronic components, traditional soldering techniques cannot be used because of their inherent sensitivity to thermal stresses. One such component is the Optoelectronic Butterfly Package which houses a laser diode chip aligned to a fibre-optic cable. Even sub-micron misalignment of the fibre optic and laser diode chip can significantly reduce the performance of the device. The high cost of each unit requires that the number of damaged components, via the laser soldering process, are kept to a minimum. Mathematical modelling is undertaken to better understand the laser soldering process and to optimize operational parameters such as solder paste volume, copper pad dimensions, laser solder times for each joint, laser intensity and absorption coefficient. Validation of the model against experimental data will be completed, and will lead to an optimization of the assembly process, through an iterative modelling cycle. This will ultimately reduce costs, improve the process development time and increase consistency in the laser soldering process.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116378198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012468
S. P. Watson, B. Sammakia
This paper describes the results of a computational investigation of the thermal performance of chip scale package arrays with various low profile heat sinks. The arrays considered were fully populated with both modules and heat sinks. The heat sinks used in any single array were identical. The parameters evaluated included module spacing, cooling air inlet velocity, per module power dissipation, and heat sink design. The heat sinks fell into two categories: the plate and the block. A plate was defined as a single continuous piece of material covering all of the modules in the array. The block heat sinks were individual pieces of material that were affixed to each module and were not physically connected to the other heat sinks in the array. The results of this study are presented as thermal resistances for each module in the array. Also considered, for some specific cases, are the heat transfer coefficients for each heat sink as a function of its position within the array. Interesting results included the changing of the shape of the resistance curve with changes in heat sink design. Also noted was the relationship between the thermal resistance of a module and the heat transfer coefficient for the top surface of that heat sink. Related to this were the changes in thermal resistance due to changes in the material properties used in the modules and how this affected the heat flow within the array.
{"title":"The thermal performance of a chip scale package array with simple block and plate heat sinks","authors":"S. P. Watson, B. Sammakia","doi":"10.1109/ITHERM.2002.1012468","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012468","url":null,"abstract":"This paper describes the results of a computational investigation of the thermal performance of chip scale package arrays with various low profile heat sinks. The arrays considered were fully populated with both modules and heat sinks. The heat sinks used in any single array were identical. The parameters evaluated included module spacing, cooling air inlet velocity, per module power dissipation, and heat sink design. The heat sinks fell into two categories: the plate and the block. A plate was defined as a single continuous piece of material covering all of the modules in the array. The block heat sinks were individual pieces of material that were affixed to each module and were not physically connected to the other heat sinks in the array. The results of this study are presented as thermal resistances for each module in the array. Also considered, for some specific cases, are the heat transfer coefficients for each heat sink as a function of its position within the array. Interesting results included the changing of the shape of the resistance curve with changes in heat sink design. Also noted was the relationship between the thermal resistance of a module and the heat transfer coefficient for the top surface of that heat sink. Related to this were the changes in thermal resistance due to changes in the material properties used in the modules and how this affected the heat flow within the array.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117003821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012440
J. DeVoe, A. Ortega
This paper outlines research aimed at testing compact thermal models in various board level environments. Results for two generic package types are presented: CPGA and a BGA. A validated fully detailed finite element model and a compact thermal model (CTM) were generated for each. A smeared finite element model of the JEDEC standard thermal test PCBs for each package was built. The boards were modeled assuming both isotropic and anisotropic effective (smeared) thermal conductivities for the PCB. The CTM and fully detailed model (FDM) for each package were "mounted" to its respective test boards. Finite element analysis was performed for each board and package system for a set of five convective boundary sets chosen to test the limits of the models. Runs were also conducted in which heated components were placed with varied proximity to the package model on a larger test board. Comparisons were made of the temperatures predicted by the package FDM/board models and the CTM/board model. The CTM models were found in general to predict junction temperatures to within 5% of the results found using the FDM of the chip packages/board in realistic cooling scenarios.
{"title":"An assessment of the behavior of compact thermal models of electronic packages in a printed circuit board level environment","authors":"J. DeVoe, A. Ortega","doi":"10.1109/ITHERM.2002.1012440","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012440","url":null,"abstract":"This paper outlines research aimed at testing compact thermal models in various board level environments. Results for two generic package types are presented: CPGA and a BGA. A validated fully detailed finite element model and a compact thermal model (CTM) were generated for each. A smeared finite element model of the JEDEC standard thermal test PCBs for each package was built. The boards were modeled assuming both isotropic and anisotropic effective (smeared) thermal conductivities for the PCB. The CTM and fully detailed model (FDM) for each package were \"mounted\" to its respective test boards. Finite element analysis was performed for each board and package system for a set of five convective boundary sets chosen to test the limits of the models. Runs were also conducted in which heated components were placed with varied proximity to the package model on a larger test board. Comparisons were made of the temperatures predicted by the package FDM/board models and the CTM/board model. The CTM models were found in general to predict junction temperatures to within 5% of the results found using the FDM of the chip packages/board in realistic cooling scenarios.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128778525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012507
R. Schmidt, E. Cruz
This paper focuses on the effect of the rack inlet temperatures resulting from chilled air exhausting from perforated tiles situated in both the hot and cold aisles of a raised floor data center. Only the above floor (raised floor) flow and temperature distributions were analyzed for various flowrates exhausting from the perforated tiles. A Computational Fluid Dynamic(CFD) model was generated for the room with electronic equipment installed on a raised floor with particular focus on the effects on rack inlet temperatures of equipment heat load, placement of air conditioning (A/C) units and chilled air flowrates. Forty racks of data processing (DP) equipment were arranged in rows in a data center cooled by chilled air exhausting from perforated floor tiles. The chilled air was provided by four A/C units placed inside a room 12.1 m wide x 13.4 m long. Since the arrangement of the racks in the data center was symmetric only one-half of the data center needed to be modeled. The numerical modeling was performed using a commercially available finite control volume computer code called Flotherm (Trademark of Flomerics, Inc.). The flow was modeled using the k-e turbulence model. Results are displayed to provide some guidance on the design and layout of a data center.
{"title":"Raised floor computer data center: effect on rack inlet temperatures of chilled air exiting both the hot and cold aisles","authors":"R. Schmidt, E. Cruz","doi":"10.1109/ITHERM.2002.1012507","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012507","url":null,"abstract":"This paper focuses on the effect of the rack inlet temperatures resulting from chilled air exhausting from perforated tiles situated in both the hot and cold aisles of a raised floor data center. Only the above floor (raised floor) flow and temperature distributions were analyzed for various flowrates exhausting from the perforated tiles. A Computational Fluid Dynamic(CFD) model was generated for the room with electronic equipment installed on a raised floor with particular focus on the effects on rack inlet temperatures of equipment heat load, placement of air conditioning (A/C) units and chilled air flowrates. Forty racks of data processing (DP) equipment were arranged in rows in a data center cooled by chilled air exhausting from perforated floor tiles. The chilled air was provided by four A/C units placed inside a room 12.1 m wide x 13.4 m long. Since the arrangement of the racks in the data center was symmetric only one-half of the data center needed to be modeled. The numerical modeling was performed using a commercially available finite control volume computer code called Flotherm (Trademark of Flomerics, Inc.). The flow was modeled using the k-e turbulence model. Results are displayed to provide some guidance on the design and layout of a data center.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128033473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012459
M. del Valle, A. M. Carrasco, A. Guzmán
This work investigates the transition scenario and heat transfer characteristics in a channel with a block tandem, as the flow evolves from a laminar to a transitional regime, by two-dimensional direct numerical simulations (DNS) of the time dependent, incompressible continuity, Navier-Stokes and energy equations. This investigation uses an extended computational domain with 10 blocks to determine the existence of a fully developed flow and self-similar temperature profiles, and a reduced computational domain to investigate the heat transfer enhancement for laminar and transitional flow regimes. This investigation demonstrates that significant heat transfer enhancements can be obtained at supercritical transitional flow Reynolds numbers with a minimum of dissipation due to viscous stresses. This enhancement is obtained without the necessity of operating this channel to high volumetric flow rates associated to turbulent flow regimes, which demand high pumping powers. In this channel, the transitional flow regime is more efficient than a laminar flow regime as a method of cooling electronics.
{"title":"Flow transitions and heat transfer in open block tandem channels","authors":"M. del Valle, A. M. Carrasco, A. Guzmán","doi":"10.1109/ITHERM.2002.1012459","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012459","url":null,"abstract":"This work investigates the transition scenario and heat transfer characteristics in a channel with a block tandem, as the flow evolves from a laminar to a transitional regime, by two-dimensional direct numerical simulations (DNS) of the time dependent, incompressible continuity, Navier-Stokes and energy equations. This investigation uses an extended computational domain with 10 blocks to determine the existence of a fully developed flow and self-similar temperature profiles, and a reduced computational domain to investigate the heat transfer enhancement for laminar and transitional flow regimes. This investigation demonstrates that significant heat transfer enhancements can be obtained at supercritical transitional flow Reynolds numbers with a minimum of dissipation due to viscous stresses. This enhancement is obtained without the necessity of operating this channel to high volumetric flow rates associated to turbulent flow regimes, which demand high pumping powers. In this channel, the transitional flow regime is more efficient than a laminar flow regime as a method of cooling electronics.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128194279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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