Identify problematic layout patterns through volume diagnosis

Abstract

Summary form only given. Due to various manufacture difficulties in nano-scale semiconductor devices, certain layout patterns cannot be manufactured properly and cause significant yield loss. Due to the time to run through complete lithography simulation, it is impossible to identify all of them before silicon manufacture. Therefore, post-silicon physical failure analysis is needed to find them one-by-one to improve yield iteratively with each re-spin. However, physical failure analysis is time-consuming such that each re-spin can take a long time. To speed-up yield ramp-up, we proposed to automatically identify as many layout patterns as possible by using volume diagnosis from post-silicon manufacture failure data. Typically volume diagnosis uses two procedures. First, responses from failing devices are analyzed using defect diagnosis tools. Next the results of diagnoses are analyzed using statistical, data mining and machine learning techniques to effectively determine the underlying problematic layout patterns. In this presentation, we will discuss the procedures and statistics methods for analyzing diagnosis data and put special attention to the link between defects and layout patterns.