Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic

Abstract

A major challenge in the design of microprocessor circuits is transistor sizing in dynamic CMOS logic due to increased number of channel-connected transistors on various paths of the design, and increased magnitude of process variations in the nanometer process. This paper proposes a process variation aware transistor sizing algorithm for dynamic CMOS logic. The efficiency of this algorithm is illustrated first by a 2-b weighted binary-to-thermometric converter, of which the critical path delay was optimized from 355 to 157 ps which accounts for a 55.77% delay improvement, and the delay uncertainty due to process variation was optimized by 60.75%. A 4-b unity weight binary-to-thermometric converter was also optimized, of which the critical path delay was reduced from 152 to 103 ps which accounts for a 32.23% delay improvement, and delay uncertainty was optimized by 63.6%. Applying the proposed timing optimization algorithm to a mixed-dynamic-static CMOS 64-bit adder, the critical path delay and the power-delay-product were optimized to 632 ps and 84.17 pJ, respectively.