C. Singh, Anisha Pathania, K. Sharma, Jaya Madan, Rajnish Sharma
{"title":"Design of an Integrator-Differentiator Block For a Transimpedance Amplifier Using $0.18\\mu \\mathrm{m}$ Technology","authors":"C. Singh, Anisha Pathania, K. Sharma, Jaya Madan, Rajnish Sharma","doi":"10.1109/DEVIC.2019.8783474","DOIUrl":null,"url":null,"abstract":"Transimpedance amplifier (TIA) has become an integral part of front-end electronics required for current sensing applications. In this paper, an integrator-differentiator block as an integral part of TIA has been reported using $\\pmb{0.18} \\mathbf{\\mu m}$ technology in standard CMOS N-well process. A tunable pseudo-resistor has been deployed in the proposed TIA architecture to obtain a variable gain and bandwidth of interest. The reported work also discusses the problem of saturation and clock feed-through present in the integrator block. The simulated gain and noise plots for the integrator-differentiator blocks are also presented in this work. Research effort put forth in this way in implementing the TIA may be helpful for efficient current recording and detection.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Devices for Integrated Circuit (DevIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DEVIC.2019.8783474","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Transimpedance amplifier (TIA) has become an integral part of front-end electronics required for current sensing applications. In this paper, an integrator-differentiator block as an integral part of TIA has been reported using $\pmb{0.18} \mathbf{\mu m}$ technology in standard CMOS N-well process. A tunable pseudo-resistor has been deployed in the proposed TIA architecture to obtain a variable gain and bandwidth of interest. The reported work also discusses the problem of saturation and clock feed-through present in the integrator block. The simulated gain and noise plots for the integrator-differentiator blocks are also presented in this work. Research effort put forth in this way in implementing the TIA may be helpful for efficient current recording and detection.