A high performance IDDQ testable cache for scaled CMOS technologies

Abstract

Quiescent supply current (IDDQ) testing is a useful test method for static CMOS RAM and can be combined with functional testing to reduce total test time and to increase reliability. However the sensitivity of IDDQ testing deteriorates significantly with technology scaling as intrinsic leakage of CMOS circuits increases. In this paper, we use a design technique for a high-performance cache, which greatly improves leakage current and hence the IDDQ testability of the cache with technology scaling. We utilize the concept of gated-ground (NMOS transistor inserted between ground line and SRAM cell) to achieve reduction in leakage energy due to the stacking effect of the transistor without significantly affecting performance. Simulation results for a 64 K cache show 20% average improvement in IDDQ sensitivity for TSMC 0.25 /spl mu/m technology, while the improvement is more than 1000% for the 70 nm predictive technology model.