{"title":"Performance of Two-Dimensional MoS2 Field-Effect Transistor in the Presence of Oxide-Channel Imperfection","authors":"Akhilesh Rawat, Anjali Goel, Brajesh Rawat","doi":"10.1109/ICEE56203.2022.10118213","DOIUrl":null,"url":null,"abstract":"In this work, we propose a more accurate description of the interface trap in the MoS2 field-effect transistor using a quantum-mechanical modeling framework. Introducing an interface trap based on tight-binding parameter substitution at an atomic site is found to be a more effective way to include its effect on the device electrostatics and the carrier transport. Further, lower energy interface traps from conduction band are found to significantly impact the device performance, with severe degradation in subthreshold slope and ON-current. Our proposed model reveals that charge trapping in the interface trap causes substantial degradation in the drive current for high gate biases, whereas source-to-drain tunneling through trap limits the performance for low gate biases.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Emerging Electronics (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEE56203.2022.10118213","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this work, we propose a more accurate description of the interface trap in the MoS2 field-effect transistor using a quantum-mechanical modeling framework. Introducing an interface trap based on tight-binding parameter substitution at an atomic site is found to be a more effective way to include its effect on the device electrostatics and the carrier transport. Further, lower energy interface traps from conduction band are found to significantly impact the device performance, with severe degradation in subthreshold slope and ON-current. Our proposed model reveals that charge trapping in the interface trap causes substantial degradation in the drive current for high gate biases, whereas source-to-drain tunneling through trap limits the performance for low gate biases.