W. De Wilde, N. Scantamburlo, M. Combe, J. Van Leeuwe, K. Doorakkers, Y. Mazoyer, C. Renous, R. Petigny, A. Bonin, B. Bayracki, B. Belhi, E. Moons, J. Sevenhans
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引用次数: 12
Abstract
A 12MHz 760mW analog front end for DMT-based VDSL integrates all active components except line driver in a single BiCMOS 0.35/spl mu/m ASIC. When fully active, the ASIC dissipates 480mW at 3.3V supply, providing resolution equivalent to 12b without trimming.
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