A single chip video coding system with embedded DRAM frame memory for stand-alone applications

K. Herrmann, J. Hilgenstock, P. Pirsch
{"title":"A single chip video coding system with embedded DRAM frame memory for stand-alone applications","authors":"K. Herrmann, J. Hilgenstock, P. Pirsch","doi":"10.1109/ASIC.1998.723023","DOIUrl":null,"url":null,"abstract":"A video coding subsystem for monolithic integration in a 0.25 /spl mu/m CMOS technology has been developed. It consists of a programmable video signal processor core, up to 8 Mbit frame memory as embedded DRAM and video interfaces. The functionality of all major components has been verified by implementation on test chips in 0.5 /spl mu/m CMOS technology. A system realization in 0.25 /spl mu/m CMOS technology is planned. Investigations show that a die size of less than 89 mm/sup 2/ for a single chip implementation can be achieved.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1998.723023","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

A video coding subsystem for monolithic integration in a 0.25 /spl mu/m CMOS technology has been developed. It consists of a programmable video signal processor core, up to 8 Mbit frame memory as embedded DRAM and video interfaces. The functionality of all major components has been verified by implementation on test chips in 0.5 /spl mu/m CMOS technology. A system realization in 0.25 /spl mu/m CMOS technology is planned. Investigations show that a die size of less than 89 mm/sup 2/ for a single chip implementation can be achieved.
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一种用于独立应用的带有嵌入式DRAM帧存储器的单芯片视频编码系统
在0.25 /spl μ m CMOS技术下,开发了一种单片集成视频编码子系统。它由一个可编程的视频信号处理器核心、高达8mbit的帧存储器作为嵌入式DRAM和视频接口组成。所有主要组件的功能已通过在0.5 /spl μ m CMOS技术的测试芯片上实现进行了验证。设计了0.25 /spl mu/m CMOS技术的系统实现方案。研究表明,可以实现小于89 mm/sup /的单芯片芯片尺寸。
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