A 4096 x 1 static bipolar RAM

Abstract

is shown in Figure 1. By eliminatingemitter base spacing, device size is significantly reduced, resulting in a memory cell size of only three square mils per cell, and a 4K RAM chip of 23,650 square mils. A photomicrograph of the chip appears in Figure 2. The small size compares very favorably with the state-ofthe-art MOS static RAM cell size. Furthermore, parasitic capacitances are reduced, improving memory performance. The cell has an emitter base capacitance of 0.05 pF, collector base capacitance of 0.09pF and collector substrate capacitance of 0.255pF. The architecture is conventional. A block diagram of the chip is shown in Figure 4. A chip select input is provided for logic flexibility. The read and write operat ics are controlled by the state of the active low write enable, WE. With R7E held low and the chip selected, the data at Din is written into the addressed location To read, WE is held high and the chip selected. Data in the specified location are presented at the data output. ECL design techniques are used throughout the internal circuitry for better speed power product. Design features are shown in Figure 5. Word line discharge circuitry provides fast word line switching. Each bit line current sink is shared by 4 bit line pairs to reduce power. Performance and power allocation of developmental samples manufactured to date are summarized in Table I and Table 11. With typical address access time of around 35 ns, these devices should find application in high performance main memory in addition to the more traditional role of scratch pad memories. Cross section of a typical walled emitter Isoplanar transistor