An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology

Jie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, M. Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, S. Sheu, Hung-Ming Chen, Kuan-Neng Chen, W. Lo, Chih-I Wu
{"title":"An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology","authors":"Jie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, M. Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, S. Sheu, Hung-Ming Chen, Kuan-Neng Chen, W. Lo, Chih-I Wu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830188","DOIUrl":null,"url":null,"abstract":"2.5D/3D integration combines multiple dies or chiplets into a single package through a silicon interposer and through-silicon-vias (TSVs). However, the wire routing of redistribution layer (RDL) on an interposer is time-consuming and expensive. Therefore, this work demonstrates the first programmable 2.5D/3D integration by an embedded multi-die active bridge (EMAB) chip for fast 2.5D/3D prototype proof. The EMAB chip is a programmable bridge and realized by a checkboard and super highways to connect I/Os of multiple dies. The control of programmable switches in EMAB is based on the information stored in the one-time programming (OTP) memory. To further improving the data rates of switches in the checkboard and super highway, a forward body-bias control is utilized to reduce the turn-on resistance. The maximum data rate of the super highway is up to 1Gbps and the data rate of the checkboard is 100Mbps through 20 I/O blocks. The proposed programmable advanced package technology is a fast time-to-market and low-cost 2.5D/3D integration solution for various IoT applications.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830188","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

2.5D/3D integration combines multiple dies or chiplets into a single package through a silicon interposer and through-silicon-vias (TSVs). However, the wire routing of redistribution layer (RDL) on an interposer is time-consuming and expensive. Therefore, this work demonstrates the first programmable 2.5D/3D integration by an embedded multi-die active bridge (EMAB) chip for fast 2.5D/3D prototype proof. The EMAB chip is a programmable bridge and realized by a checkboard and super highways to connect I/Os of multiple dies. The control of programmable switches in EMAB is based on the information stored in the one-time programming (OTP) memory. To further improving the data rates of switches in the checkboard and super highway, a forward body-bias control is utilized to reduce the turn-on resistance. The maximum data rate of the super highway is up to 1Gbps and the data rate of the checkboard is 100Mbps through 20 I/O blocks. The proposed programmable advanced package technology is a fast time-to-market and low-cost 2.5D/3D integration solution for various IoT applications.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于快速原型可编程2.5D/3D封装技术的嵌入式多模有源桥接(EMAB)芯片
2.5D/3D集成将多个晶片或芯片通过硅中间层和硅通孔(tsv)集成到单个封装中。然而,中间层上的重新分配层(RDL)的布线既耗时又昂贵。因此,这项工作通过嵌入式多模有源电桥(EMAB)芯片演示了第一个可编程2.5D/3D集成,用于快速2.5D/3D原型验证。EMAB芯片是一个可编程的桥接电路,通过棋盘和高速公路实现多个芯片的I/ o连接。EMAB中可编程开关的控制是基于存储在一次性编程(OTP)存储器中的信息。为了进一步提高检查板和高速公路上的开关的数据速率,采用正向体偏控制来减小导通电阻。高速公路的最大数据速率可达1Gbps,通过20个I/O块,校验板的数据速率可达100Mbps。提出的可编程先进封装技术是一种快速上市和低成本的2.5D/3D集成解决方案,适用于各种物联网应用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1