An EPC Class-1 Generation-2 baseband processor for passive UHF RFID tag

Abstract

Passive UHF RFID transponders (tags, in short) are mixed-signal Systems-on-Chip (SoCs) for remotely powered communications which must comply with stringent requirements on current consumption. This brief focuses on the design of a backend digital processor for UHF RFID tags targeting the Class-1 Generation- 2 EPC Protocol, and proposes different techniques for reducing its power consumption. After code validation with an FPGA, the processor has been synthetised in a 0.35µm CMOS technology process and occupies 7mm2 including pads. The design also incorporates a 10-b rail-to-rail SAR ADC for sensory applications. Under maximum digital activity conditions, post-layout simulations show that the power consumption of the processor below 2.8µW.