Pattern design criteria of main circuit using printed circuit boards for parasitic inductance reduction

Abstract

This paper investigates differences of parasitic inductances caused by DC bus bar patterns on printed circuit boards(PCB). The DC bus bar pattern on the PCB is limited depending on the layout of main circuits and the control circuits. Two patterns which are a laminated wiring pattern and a plane wiring pattern are compared in experiments and simulations. In this paper, it will be clarified that effects of the DC bus bars on PCBs such as a surge voltage of a switch in terms of the parasitic inductance depending on the circuits on PCBs. As a result, if the same parasitic inductance which is 20 nH, is realized between each wiring pattern at the same length, the plane wiring pattern requires over ten times of the pattern width compared with that of the laminated wiring pattern. Hence, the circuit size can be downsized when the laminated pattern is used. From the experimental results, the maximum surge voltage in the plane wiring pattern is larger than that in the laminated wiring pattern. In this case, the parasitic inductance value of the plane wiring pattern is three times that of the laminated wiring pattern. However, the surge voltage in the laminated pattern is reduced by 7% compared with the plane wiring pattern. As a consequence, the ratio of the surge voltage does not match that of the parasitic inductance. As a result, not only the parasitic inductance of the DC bus bar but also it is necessary to consider other parasitic inductances on PCBs such as parasitic inductances into input capacitors and the path between an upper MOSFET and a lower one and so on.