Werda Imen, Belghith Fatma, Maraoui Amna, N. Masmoudi
{"title":"DCT -II Transform Hardware-Based Acceleration for VVC Standard","authors":"Werda Imen, Belghith Fatma, Maraoui Amna, N. Masmoudi","doi":"10.1109/DTS52014.2021.9498196","DOIUrl":null,"url":null,"abstract":"The versatile video coding (VVC) standard achieves an important coding efficiency performance due to relevant innovation induced within several tools. Numerous contributions were made to the transform module with the use of new approach called Multiple Transform Selection (MTS). Three transform types are allowed: two Discrete Cosine Transform (DCT), noted DCT-II and DCT-VIII ; and one Discrete Sine Transforms (DST) DST-VII. This novel module enhances the compression efficiency performance and induces additional computational complexity. This work proposes hardware architectures of the 1-D and 2-D DCT-II transform considered as the most selected transform type within MTS module. Proposed implementation exploits correlation and symmetry properties within DCT-II transform matrices. VHDL implementation of the adopted method was able to process at 164 MHZ under an Arria 10AX115N3F4512SGES device.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTS52014.2021.9498196","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
The versatile video coding (VVC) standard achieves an important coding efficiency performance due to relevant innovation induced within several tools. Numerous contributions were made to the transform module with the use of new approach called Multiple Transform Selection (MTS). Three transform types are allowed: two Discrete Cosine Transform (DCT), noted DCT-II and DCT-VIII ; and one Discrete Sine Transforms (DST) DST-VII. This novel module enhances the compression efficiency performance and induces additional computational complexity. This work proposes hardware architectures of the 1-D and 2-D DCT-II transform considered as the most selected transform type within MTS module. Proposed implementation exploits correlation and symmetry properties within DCT-II transform matrices. VHDL implementation of the adopted method was able to process at 164 MHZ under an Arria 10AX115N3F4512SGES device.