Reliability Challenges in Advanced 3D Technologies: The Case of Through Silicon Vias and SiCN–SiCN Wafer-to-Wafer Hybrid-Bonding Technologies

Abstract

As the traditional more Moore approach is slowing down, due to the increase in development costs and logic complexity, 3D technologies are enabling complex More than Moore Systems-on-Chip (SoC), offering higher performances and functionalities to customers. 3D SoC combine efficiently chips from different technology nodes through vertical interconnections, enabling complex designs out of reach of the monolithic approach. Vertical interconnection technologies are therefore key enablers of the More than Moore paradigm, allowing higher densities with reduced latencies. In particular, through silicon vias (TSV) and wafer-to-wafer hybrid bonding will be key to the success of the next generation of 3D Systems-on-Chip by bringing the interconnect densities above 106 mm−2. In this article, the reliability challenges and failure mechanisms related to these two technologies are reviewed and potential mitigation solutions developed at imec are introduced. In the first section, the process and technology choices enabling the TSV and SiCN–SiCN wafer-to-wafer hybrid-bonding technologies are summarized. Subsequently, the impact of mechanical stress and liner integrity on the reliability of TSVs are discussed. In this context, it is shown that copper poisoning in the dielectric during the liner opening etch is a major challenge, requiring careful optimization of the etch recipe. A lifetime assessment of the hybrid-bonding pad-to-pad interface is then presented. The importance of a soft CMP process, that minimizes the degradation of the bonding dielectric and therefore the creation of defects is demonstrated. Additionally, the impact of copper migration along the bonding interface on the reliability performance is mentioned. Finally, the role of bonding voids in the electromigration performances of copper pads will be discussed.