Design and Development of Effective Multi-Level Cache Memory Model

Eze Val Hyginus Udoka, Martin Chinweokwu Eze, Enerst Edozie, Esther Chidinma Eze
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Abstract

An algorithm to determine the effectiveness and efficiency of a multi-level cache was developed in this paper. The developed model was used to test the efficiency rate, the relationships and the performance output level of a computer concerning the cache properties. This research paper showed that the level of cache and access time increases with the absolute hit rate but decreases with the relative hit rate. The number of cache levels varies directly with absolute access time and inversely with relative access time. The level one cache with set associativity of one has the highest access time and as the associativity and cache levels increase the memory access time decreases. The increase in the number of set associativity leads to an increase in cache performance and as well increases the performance speed of a computer.
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高效多级高速缓存存储器模型的设计与开发
本文提出了一种确定多级缓存有效性和效率的算法。利用所建立的模型测试了计算机在缓存性能方面的效率、关系和性能输出水平。研究表明,缓存级别和访问时间随着绝对命中率的增加而增加,而随着相对命中率的增加而减少。缓存级别的数量与绝对访问时间成正比,与相对访问时间成反比。结合性为1的第一级缓存具有最高的访问时间,并且随着结合性和缓存级别的增加,内存访问时间减少。集合结合性数量的增加导致缓存性能的提高,同时也提高了计算机的性能速度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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