Design and Comparison of Low Power Consumption Binary and Quaternary Multipliers

Abstract

There is a rapid growth in semiconductor technology as the need for digital application systems has  increased. Arithmetic operations such as addition and multiplication play a major role in DSP applications. As a result, there is thorough research on various methods to achieve high-speed and low-power DSP applications. In multipliers, the Vedic multiplier is considered as a fast multiplier because of its consistent structure resulting in low power consumption. Array multiplier is implemented with half and full adders. This kind of implementation of the array multiplier needs the previous output to provide the last word output, which leads to an increase in delay. In DSP applications, the key problem corresponds to carry generation delay. To overcome the delay, a carry-lookahead adder is used. In this work, a Vedic multiplier using a carry-lookahead adder is used with quaternary logic in the CMOS process. The width and length of the transistors are defined as 1.7 µm (PMOS), 850 nm (NMOS), and 180 nm for 1.8 V supply in 180 nm CMOS process. Simulation results show that the designed Vedic multiplier enhances the performance when compared with the conventional multiplier.