A 4.24-GHz 128×256 SRAM Operating Double Pump Read Write Same Cycle in 5-nm Technology

Abstract

A High-Speed High-Density 1R1W two port 32Kbit ( $128\times 256$ ) SRAM with single port 6T bitcell macro is proposed. A read-then-write (RTW) double pump CLK generation circuit with tracking bitline (TRKBL) bypassing is proposed to boost read and write performance. A local interlock circuit (LIC) is introduced in Sense-Amp to reduce active power and push Fmax further. To mitigate metal RC degradation, double metal scheme is applied to improve signal integrity and enhance overall operating cycle time. The silicon results show that the slow corner wafer was able to achieve 4.24 GHz at 1.0 V/100 °C in 5-nm FinFET technology.