Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

Abstract

This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel. For the analysis, three different channel structures are used: (a) tri-layer stack channel (TLSC) (Si–SiGe–Si), (b) double layer stack channel (DLSC) (SiGe–Si), (c) single layer channel (SLC) (Si). The I−V characteristics, subthreshold swing (SS), drain-induced barrier lowering (DIBL), threshold voltage (V _t), drain current (I _ON), OFF current (I _OFF), and ON-OFF current ratio (I _ON/I _OFF) are observed for the structures at a 20 nm gate length. It is seen that TLSC provides 21.3% and 14.3% more ON current than DLSC and SLC, respectively. The paper also explores the analog and RF factors such as input transconductance (g _m), output transconductance (g _ds), gain (g _m/g _ds), transconductance generation factor (TGF), cut-off frequency (f _T), maximum oscillation frequency (f _max), gain frequency product (GFP) and linearity performance parameters such as second and third-order harmonics (g _m2, g _m3), voltage intercept points (VIP₂, VIP₃) and 1-dB compression points for the three structures. The results show that the TLSC has a high analog performance due to more g _m and provides 16.3%, 48.4% more gain than SLC and DLSC, respectively and it also provides better linearity. All the results are obtained using the VisualTCAD tool.