Reliable and ultra-low power approach for designing of logic circuits

Abstract

The principal design concern in today’s very large-scale integration (VLSI) industry is power dissipation. Power dissipation in a chip rises reliability issues. Static power dissipation places a bottleneck in scaling down the dimensions and supply voltage of metal oxide semiconductor field effect transistor (MOSFET). Short channel effects (SCEs) put a limit on MOSFET scaling. At the lower technology nodes, the control of the gate over the channel is lost in MOSFET. Fin-shaped field effect transistor (FinFETs) uses multiple gates to gain much electrostatic control over the channel. FinFET not only improves the drive current but also reduces the subthreshold leakage. This paper proposes a novel power-efficient technique for the nanoscale regime. The simulation results are derived using Mentor Graphics at a 16 nm node. The power is reduced by 91.45% and 89.01% in the proposed MOSFET and FinFET-based inverter, respectively. A chain of 5-inverters is designed as a benchmark circuit to check the performance comparisons. In the proposed MOSFET and FinFET-based benchmark circuit, there is a power delay product (PDP) reduction of 80.28%, and 99.87%, respectively. The effect of process voltage and temperature (PVT) variations for the robustness of the technique is also discussed. The proposed technique provides the power-efficient and robustness operation against the variations as compared to the other methods.