Analysis and circuit design of isolated forward SEPIC converter with minimum-phase stability

Abstract

Purpose

Conventional isolated dc–dc converters offer an efficient solution for performing voltage conversion with a large improved voltage gain. However, the small-signal analysis of these converters shows that a right-half-plane (RHP) zero appears in their control-to-output transfer function, exhibiting a nonminimum-phase stability. This RHP zero can limit the frequency response and dynamic specifications of the converters; therefore, the output voltage response is sluggish. To overcome these problems, the purpose of this study is to analyze, model and design a new isolated forward single-ended primary-inductor converter (IFSEPIC) through RHP zero alleviation.

Design/methodology/approach

At first, the normal operation of the suggested IFSEPIC is studied. Then, its average model and control-to-output transfer function are derived. Based on the obtained model and Routh–Hurwitz criterion, the components are suitably designed for the proposed IFSEPIC, such that the derived dynamic model can eliminate the RHP zero.

Findings

The advantages of the proposed IFSEPIC can be summarized as: This converter can provide conditions to achieve fast dynamic behavior and minimum-phase stability, owing to the RHP zero cancellation; with respect to conventional isolated converters, a larger gain can be realized using the proposed topology; thus, it is possible to attain a smaller operating duty cycle; for conventional isolated converters, transformer core saturation is a major concern, owing to a large magnetizing current. However, the average value of the magnetizing current becomes zero for the proposed IFSEPIC, thereby avoiding core saturation, particularly at high frequencies; and the input current of the proposed converter is continuous, reducing input current ripple.

Originality/value

The key benefits of the proposed IFSEPIC are shown via comparisons. To validate the design method and theoretical findings, a practical implementation is presented.