N. Zerhouni Abdou , S. Reboh , L. Brunet , M. Alepidis , P. Acosta Alba , S. Cristoloveanu , I. Ionica
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引用次数: 0
Abstract
The junctionless EZ-FET is a simple FDSOI-like device that requires only two lithography levels and standard processing steps. With its simplified architecture and fabrication flow, and using undoped source and drain terminals, the device allows for a fast electrical evaluation of semiconductor films on insulators (SOI) and gate stacks. This paper describes an electrical model that reproduces the peculiar transfer characteristics of a junctionless EZ-FET. The model is then simplified to develop a pragmatic parameter extraction methodology. This methodology is experimentally validated and provides the electrical properties of SOI films (mobility, threshold voltage) for both electrons and holes.
期刊介绍：
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.
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