Pub Date : 2025-04-10DOI: 10.1016/j.sse.2025.109113
Jaehyun Lee
This study investigates the variability induced by random discrete dopants (RDDs) in the source and drain extension (SDE) regions in cryogenic -type gate-all-around nanosheet field-effect transistors using the extensive quantum transport simulations. RDDs in the SDE regions effectively alter the channel length, necessitating a detailed analysis of the temperature dependence of short channel effects across a range from cryogenic (77 K) to room temperature (300 K). The results clearly demonstrate that cryogenic devices are more susceptible to random dopant fluctuation (RDF), exhibiting greater variability in threshold voltage, ON-state current, and drain-induced barrier lowering compared to devices operating at 300 K, even when the intrinsic channel device is considered. These findings emphasize the importance of rigorously addressing local variability, such as RDF, alongside process-induced variability in the design and optimization of cryogenic devices and associated circuits.
{"title":"Investigating random discrete dopant-induced variability in cryogenic gate-all-around nanosheet FETs: A quantum transport simulation study","authors":"Jaehyun Lee","doi":"10.1016/j.sse.2025.109113","DOIUrl":"10.1016/j.sse.2025.109113","url":null,"abstract":"<div><div>This study investigates the variability induced by random discrete dopants (RDDs) in the source and drain extension (SDE) regions in cryogenic <span><math><mi>n</mi></math></span>-type gate-all-around nanosheet field-effect transistors using the extensive quantum transport simulations. RDDs in the SDE regions effectively alter the channel length, necessitating a detailed analysis of the temperature dependence of short channel effects across a range from cryogenic (77 K) to room temperature (300 K). The results clearly demonstrate that cryogenic devices are more susceptible to random dopant fluctuation (RDF), exhibiting greater variability in threshold voltage, ON-state current, and drain-induced barrier lowering compared to devices operating at 300 K, even when the intrinsic channel device is considered. These findings emphasize the importance of rigorously addressing local variability, such as RDF, alongside process-induced variability in the design and optimization of cryogenic devices and associated circuits.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109113"},"PeriodicalIF":1.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we proposed a machine learning approach to assist the TCAD results in realizing a local cost and time-effective simulator for analyzing the performance metric of the vertically stacked Nanosheet FET (NSFET). The corners are responsible for field crowding inside the sheets, which significantly affects the parasitic capacitance and thereby reduces the ION/Cgg ratio. Thus, a detailed insight into corner radii optimization is worth needed. We used Sentaurus TCAD to obtain the results and further realized a local simulator using an XGBoost model to analyze process variations and the role of uneven radii corners in NSFET. In addition, a data augmentation strategy is proposed that leverages the powers of stacked autoencoders (SAE) and InfoGANs to enhance data generalization, improving model robustness and predictive reliability.
{"title":"Machine learning augmented TCAD assessment of corner radii in nanosheet FET","authors":"Jyoti Patel , Bathula Satwik , Navjeet Bagga , Ishani Bais , Chirag Arora , Vivek Kumar , Ankit Dixit , Naveen Kumar , Vihar Georgiev , S. Dasgupta","doi":"10.1016/j.sse.2025.109114","DOIUrl":"10.1016/j.sse.2025.109114","url":null,"abstract":"<div><div>In this paper, we proposed a machine learning approach to assist the TCAD results in realizing a local cost and time-effective simulator for analyzing the performance metric of the vertically stacked Nanosheet FET (NSFET). The corners are responsible for field crowding inside the sheets, which significantly affects the parasitic capacitance and thereby reduces the I<sub>ON</sub>/C<sub>gg</sub> ratio. Thus, a detailed insight into corner radii optimization is worth needed. We used Sentaurus TCAD to obtain the results and further realized a local simulator using an XGBoost model to analyze process variations and the role of uneven radii corners in NSFET. In addition, a data augmentation strategy is proposed that leverages the powers of stacked autoencoders (SAE) and InfoGANs to enhance data generalization, improving model robustness and predictive reliability.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109114"},"PeriodicalIF":1.4,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143792185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1016/j.sse.2025.109122
Tabrez Qureshi , Khursheed Ahmad Sheikh , Mohammad Mohsin Khan , Harveer Singh Pali , Md Tasnim
Thermoelectric generators harness human body heat to power wearable electronic devices and are crucial for developing self-sustaining wearable systems for health and environmental monitoring. This research focuses on optimizing the power output of body heat-driven wearable thermoelectric generators, while ensuring user comfort. It emphasizes minimizing heat loss, maintaining a significant temperature differential across the thermoelectric material, and designing compact generators. Investigations explored temperature-regulated hot surfaces at various body sites including the wrist, upper arm, and chest. Power levels were recorded during activities such as running and walking. Findings indicate that power generation was most effective at the upper arm, peaking at 71.2 millivolts with a thermoelectric generator equipped with a heat sink silver spreader and silicon insulator during summer conditions. The study also evaluated the feasibility of using upper arm thermoelectric generators to power wearable electrocardiogram sensors. In comparison, while thermoelectric generators at the wrist benefited from airflow in winter, achieving up to 29.3 millivolts, those at the chest showed superior power output. This research underscores the potential of strategically placed thermoelectric generators in enhancing the functionality of wearable technologies.
{"title":"Exploring TEG parameters for optimal body heat harvesting in wearable devices","authors":"Tabrez Qureshi , Khursheed Ahmad Sheikh , Mohammad Mohsin Khan , Harveer Singh Pali , Md Tasnim","doi":"10.1016/j.sse.2025.109122","DOIUrl":"10.1016/j.sse.2025.109122","url":null,"abstract":"<div><div>Thermoelectric generators harness human body heat to power wearable electronic devices and are crucial for developing self-sustaining wearable systems for health and environmental monitoring. This research focuses on optimizing the power output of body heat-driven wearable thermoelectric generators, while ensuring user comfort. It emphasizes minimizing heat loss, maintaining a significant temperature differential across the thermoelectric material, and designing compact generators. Investigations explored temperature-regulated hot surfaces at various body sites including the wrist, upper arm, and chest. Power levels were recorded during activities such as running and walking. Findings indicate that power generation was most effective at the upper arm, peaking at 71.2 millivolts with a thermoelectric generator equipped with a heat sink silver spreader and silicon insulator during summer conditions. The study also evaluated the feasibility of using upper arm thermoelectric generators to power wearable electrocardiogram sensors. In comparison, while thermoelectric generators at the wrist benefited from airflow in winter, achieving up to 29.3 millivolts, those at the chest showed superior power output. This research underscores the potential of strategically placed thermoelectric generators in enhancing the functionality of wearable technologies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109122"},"PeriodicalIF":1.4,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143799918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1016/j.sse.2025.109119
Shuhan Wang , Zheng Zhou , Zili Tang , Jinghan Xu , Xiaoyan Liu , Xing Zhang
Efficient and accurate variation modeling serves as a critical part in circuit evaluation, which can reproduce actual electrical behavior of semiconductor devices. Conventional variation modeling usually consists of two steps: compact modeling the basic electrical properties and sub-modeling the variation sources introduced in MOSFET manufacturing process, mostly structural and doping parameters. This lengthy process results in a gap between device production and rapid circuit analysis. In order to improve modeling efficiency, in this work, we propose a one-step variation-included compact modeling approach leveraging machine learning. Utilizing conditional variational autoencoder (cVAE), currents with variation are directly constructed without the sub-modeling step, as variation sources of the cVAE model are automatically extracted. Benchmark against prior distribution of dataset generated by Monte Carlo simulation of BSIM-CMG, normalized variation in figure of merits (FoMs) of cVAE generated I-V curves are all above 0.9. After implementing the model in SPICE, high accuracy in circuit-level variation modeling also indicates the potential of the proposed model.
{"title":"One-step variation included compact modeling with conditional variational autoencoder","authors":"Shuhan Wang , Zheng Zhou , Zili Tang , Jinghan Xu , Xiaoyan Liu , Xing Zhang","doi":"10.1016/j.sse.2025.109119","DOIUrl":"10.1016/j.sse.2025.109119","url":null,"abstract":"<div><div>Efficient and accurate variation modeling serves as a critical part in circuit evaluation, which can reproduce actual electrical behavior of semiconductor devices. Conventional variation modeling usually consists of two steps: compact modeling the basic electrical properties and sub-modeling the variation sources introduced in MOSFET manufacturing process, mostly structural and doping parameters. This lengthy process results in a gap between device production and rapid circuit analysis. In order to improve modeling efficiency, in this work, we propose a one-step variation-included compact modeling approach leveraging machine learning. Utilizing conditional variational autoencoder (cVAE), currents with variation are directly constructed without the sub-modeling step, as variation sources of the cVAE model are automatically extracted. Benchmark against prior distribution of dataset generated by Monte Carlo simulation of BSIM-CMG, normalized variation in figure of merits (FoMs) of cVAE generated I-V curves are all above 0.9. After implementing the model in SPICE, high accuracy in circuit-level variation modeling also indicates the potential of the proposed model.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109119"},"PeriodicalIF":1.4,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143777167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The maximum, effective, and average thermal resistance (RTH) of AlGaN/GaN and InAlN/GaN high-electron mobility transistors (HEMTs) on silicon carbide (SiC), silicon (Si), and sapphire substrates are reported using TCAD simulation. After validating simulated I-V properties, RTH is deduced from self-heating (SH)-induced rise in channel temperature (ΔT) versus dissipated power (PD) plot. The maximum thermal resistance (RTHmax) determines HEMT reliability at higher power dissipation; so, peak channel temperature (Tmax) is extracted. The simulated ΔTmax-PD plots are compared with the literature results for each HEMT structure. The estimated RTHmax is consistent with the reported experimental values, verifying the TCAD model and confirming the validity of reported RTH values. The effective thermal resistance (RTHeff) is needed to simulate the electrical properties using the compact model. For this purpose, isothermal IDS-VDS simulations are carried out at different temperatures without SH effects. Then, the cross-over temperature points (ΔTeff) are identified by evaluating the isothermal data with the actual output properties at a particular PD. The average thermal resistance (RTHavg) of the HEMT is computed by averaging the lattice temperature profile along the channel (mean channel temperature), and RTHavg is compared with RTHeff.
{"title":"Maximum, effective, and average thermal resistance for GaN-based HEMTs on SiC, Si and sapphire substrates","authors":"Kaushik Shivanand Powar , Venkata Komalesh Tadepalli , Vaidehi Vijay Painter , Raphael Sommet , Anjan Chakravorty , P. Vigneshwara Raja","doi":"10.1016/j.sse.2025.109121","DOIUrl":"10.1016/j.sse.2025.109121","url":null,"abstract":"<div><div>The maximum, effective, and average thermal resistance (<em>R<sub>TH</sub></em>) of AlGaN/GaN and InAlN/GaN high-electron mobility transistors (HEMTs) on silicon carbide (SiC), silicon (Si), and sapphire substrates are reported using TCAD simulation. After validating simulated I-V properties, <em>R<sub>TH</sub></em> is deduced from self-heating (SH)-induced rise in channel temperature (Δ<em>T</em>) versus dissipated power (<em>P<sub>D</sub></em>) plot. The maximum thermal resistance (<em>R<sub>THmax</sub></em>) determines HEMT reliability at higher power dissipation; so, peak channel temperature (<em>T<sub>max</sub></em>) is extracted. The simulated Δ<em>T<sub>max</sub></em><strong>-</strong><em>P<sub>D</sub></em> plots are compared with the literature results for each HEMT structure. The estimated <em>R<sub>THmax</sub></em> is consistent with the reported experimental values, verifying the TCAD model and confirming the validity of reported <em>R<sub>TH</sub></em> values. The effective thermal resistance (<em>R<sub>THeff</sub></em>) is needed to simulate the electrical properties using the compact model. For this purpose, isothermal <em>I<sub>DS</sub></em>-<em>V<sub>DS</sub></em> simulations are carried out at different temperatures without SH effects. Then, the cross-over temperature points (Δ<em>T<sub>eff</sub></em>) are identified by evaluating the isothermal data with the actual output properties at a particular <em>P<sub>D</sub></em>. The average thermal resistance (<em>R<sub>THavg</sub></em>) of the HEMT is computed by averaging the lattice temperature profile along the channel (mean channel temperature), and <em>R<sub>THavg</sub></em> is compared with <em>R<sub>THeff</sub></em>.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109121"},"PeriodicalIF":1.4,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143777168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-02DOI: 10.1016/j.sse.2025.109120
L. Benichou , F. Mazen , T. Salvetat , F. Madeira , F. Rieutord
Stress management in freestanding silicon thin films obtained through ion implantation-induced delamination is investigated. Residual stress is measured through curvature of the rolled film. With a proper thermal annealing process, we can effectively relax this stress, facilitating the film manipulation and transfer. The measurements reveal a slight stress discrepancy between freestanding films and donor wafers which is discussed. The delamination of freestanding membranes opens up new possibilities for Smart-Cut™ technology on various applications.
{"title":"Stress management in freestanding membranes obtained by ion implantation induced delamination","authors":"L. Benichou , F. Mazen , T. Salvetat , F. Madeira , F. Rieutord","doi":"10.1016/j.sse.2025.109120","DOIUrl":"10.1016/j.sse.2025.109120","url":null,"abstract":"<div><div>Stress management in freestanding silicon thin films obtained through ion implantation-induced delamination is investigated. Residual stress is measured through curvature of the rolled film. With a proper thermal annealing process, we can effectively relax this stress, facilitating the film manipulation and transfer. The measurements reveal a slight stress discrepancy between freestanding films and donor wafers which is discussed. The delamination of freestanding membranes opens up new possibilities for Smart-Cut™ technology on various applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109120"},"PeriodicalIF":1.4,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143792186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-01DOI: 10.1016/j.sse.2025.109112
A. Lombrez , A. Divay , H. Boutry , L. Colas , N. Coudurier , S. Altazin , T. Baron
We report the results of a TLM-based numerical extraction methodology applied on CMOS-compatible N+-InGaAs ohmic contacts integrated with dielectrics on 200mm Si substrates. The methodology is first described and calibrated using contacts on SOI. Then, we applied this method on W/TiN/Ti on N+-InGaAs contacts to obtain state-of-the-art level ρc = 7,5.10-8 Ω.cm2 for 0.35x0.35µm contact dimension, which is close to relevant contact size of the targeted application (THz HBT for 6G).
{"title":"TLM-based numerical extraction for CMOS-compatible N+-InGaAs ohmic contacts on 200mm Si substrates","authors":"A. Lombrez , A. Divay , H. Boutry , L. Colas , N. Coudurier , S. Altazin , T. Baron","doi":"10.1016/j.sse.2025.109112","DOIUrl":"10.1016/j.sse.2025.109112","url":null,"abstract":"<div><div>We report the results of a TLM-based numerical extraction methodology applied on CMOS-compatible N<sup>+</sup>-InGaAs ohmic contacts integrated with dielectrics on 200mm Si substrates. The methodology is first described and calibrated using contacts on SOI. Then, we applied this method on W/TiN/Ti on N<sup>+</sup>-InGaAs contacts to obtain state-of-the-art level ρ<sub>c</sub> = 7,5.10<sup>-8</sup> Ω.cm<sup>2</sup> for 0.35x0.35µm contact dimension, which is close to relevant contact size of the targeted application (THz HBT for 6G).</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109112"},"PeriodicalIF":1.4,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143817080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-31DOI: 10.1016/j.sse.2025.109117
Talha Chohan , Zhixing Zhao , Luca Pirro , Loren Dombroske , Jacob Ong , Olaf Zimmerhackl , Steffen Lehmann , David Pritchard , Tao Xue , Jan Hoentschel
The coupling (crosstalk) between devices through substrate is a limiting factor for the highly integrated mixed-mode and high frequency circuits. Silicon–On–Insulator (SOI) wafer with buried oxide (BOX) inherits better low frequency isolation compared to bulk silicon. However, at higher frequencies the advantage subsides due to capacitive coupling. For the mixed mode applications, the abrupt signal switching in digital circuitry poses a detrimental effect on the noise-sensitive analog circuitry. This work studies the crosstalk isolation in commercial SOI resistivity substrate (∼1–100 Ω.cm) by deploying design-based approaches for crosstalk reduction. A clear advantage of SOI vs standard bulk is reported especially for low-frequency range. Substrate well variance with different types of junctions is studied and demonstrated to reduce noise isolation. Moreover, a novel guard-ring scheme deploying the combination of resistive and capacitive elements has shown to have improvement in the noise isolation for wide band applications compared to the individual elements.
{"title":"Substrate crosstalk characterization for optimized isolation in FDSOI","authors":"Talha Chohan , Zhixing Zhao , Luca Pirro , Loren Dombroske , Jacob Ong , Olaf Zimmerhackl , Steffen Lehmann , David Pritchard , Tao Xue , Jan Hoentschel","doi":"10.1016/j.sse.2025.109117","DOIUrl":"10.1016/j.sse.2025.109117","url":null,"abstract":"<div><div>The coupling (crosstalk) between devices through substrate is a limiting factor for the highly integrated mixed-mode and high frequency circuits. Silicon–On–Insulator<!--> <!-->(SOI) wafer with buried oxide (BOX) inherits better low frequency isolation compared to bulk silicon. However, at higher frequencies the advantage subsides due to capacitive coupling. For the mixed mode applications, the abrupt signal switching in digital circuitry poses a detrimental effect on the noise-sensitive analog circuitry. This work studies the crosstalk isolation in commercial SOI resistivity substrate (∼1–100 Ω.cm) by deploying design-based approaches for crosstalk reduction. A clear advantage of SOI vs standard bulk is reported especially for low-frequency range. Substrate well variance with different types of junctions is studied and demonstrated to reduce noise isolation. Moreover, a novel guard-ring scheme deploying the combination of resistive and capacitive elements has shown to have improvement in the noise isolation for wide band applications compared to the individual elements.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109117"},"PeriodicalIF":1.4,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-28DOI: 10.1016/j.sse.2025.109115
Michelly de Souza , Jaime Calçade Rodrigues , Lucas Mota Barbosa da Silva , Flavio Enrico Bergamaschi , Mikaël Cassé , Sylvain Barraud , Olivier Faynot , Marcelo Antonio Pavanello
In this study, an experimental assessment of transport parameters in 7-level stacked nanosheet GAA nMOSFETs is conducted, employing the Y-Function methodology to extract carrier mobility. Specifically, the contribution of horizontal and vertical conduction planes to mobility and degradation factors is investigated for transistors with varying channel lengths and nanosheet widths. The findings reveal that while overall low-field mobility demonstrates weak dependency on nanosheet width, it suffers some reduction in short-channel transistors. Furthermore, the mobility degradation was analyzed, and the results indicate that overall mobility degradation coefficients depend on the nanosheet width, as the balance between horizontal and vertical contributions varies. Notably, while the linear degradation factor dominates the mobility degradation at horizontal planes, vertical planes exhibit a dominant quadratic degradation factor. This suggests larger surface roughness scattering at sidewalls compared to horizontal planes.
{"title":"Analysis of electron mobility in 7-level stacked nanosheet GAA nMOSFETs","authors":"Michelly de Souza , Jaime Calçade Rodrigues , Lucas Mota Barbosa da Silva , Flavio Enrico Bergamaschi , Mikaël Cassé , Sylvain Barraud , Olivier Faynot , Marcelo Antonio Pavanello","doi":"10.1016/j.sse.2025.109115","DOIUrl":"10.1016/j.sse.2025.109115","url":null,"abstract":"<div><div>In this study, an experimental assessment of transport parameters in 7-level stacked nanosheet GAA nMOSFETs is conducted, employing the Y-Function methodology to extract carrier mobility. Specifically, the contribution of horizontal and vertical conduction planes to mobility and degradation factors is investigated for transistors with varying channel lengths and nanosheet widths. The findings reveal that while overall low-field mobility demonstrates weak dependency on nanosheet width, it suffers some reduction in short-channel transistors. Furthermore, the mobility degradation was analyzed, and the results indicate that overall mobility degradation coefficients depend on the nanosheet width, as the balance between horizontal and vertical contributions varies. Notably, while the linear degradation factor dominates the mobility degradation at horizontal planes, vertical planes exhibit a dominant quadratic degradation factor. This suggests larger surface roughness scattering at sidewalls compared to horizontal planes.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109115"},"PeriodicalIF":1.4,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143785792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-25DOI: 10.1016/j.sse.2025.109105
Miltiadis K. Nakos , Andreas Tsormpatzoglou , Dimitrios H. Tassis , Theodoros A. Oproglidis , Constantinos T. Angelis , Charalabos A. Dimitriadis
In this study, we investigate the impact of the source and drain (S/D) underlap regions on the electrical characteristics of short-channel double-gate junctionless transistors (DG JLTs). Analytical expression for the potential distribution in the gate overlap and S/D underlap regions is introduced, which relies on a single fitting parameter and the gate fringe capacitance in the underlap regions. The derived potential distribution shows good agreement with simulation results across different underlap lengths and gate/drain bias voltages. Consequently, new expressions for the threshold voltage and the subthreshold swing coefficient of DG JLTs are developed comprising the effect of the S/D underlap regions, which are used for upgrading our previous continuous and symmetric analytical drain current compact model. The findings highlight the significant influence of the S/D underlap regions on the electrical characteristics of DG JLTs, suggesting a need for their careful consideration in drain current compact modeling.
{"title":"Analytical modeling of nanoscale double-gate junctionless transistors comprising the impact of the source and drain underlap regions","authors":"Miltiadis K. Nakos , Andreas Tsormpatzoglou , Dimitrios H. Tassis , Theodoros A. Oproglidis , Constantinos T. Angelis , Charalabos A. Dimitriadis","doi":"10.1016/j.sse.2025.109105","DOIUrl":"10.1016/j.sse.2025.109105","url":null,"abstract":"<div><div>In this study, we investigate the impact of the source and drain (S/D) underlap regions on the electrical characteristics of short-channel double-gate junctionless transistors (DG JLTs). Analytical expression for the potential distribution in the gate overlap and S/D underlap regions is introduced, which relies on a single fitting parameter and the gate fringe capacitance in the underlap regions. The derived potential distribution shows good agreement with simulation results across different underlap lengths and gate/drain bias voltages. Consequently, new expressions for the threshold voltage and the subthreshold swing coefficient of DG JLTs are developed comprising the effect of the S/D underlap regions, which are used for upgrading our previous continuous and symmetric analytical drain current compact model. The findings highlight the significant influence of the S/D underlap regions on the electrical characteristics of DG JLTs, suggesting a need for their careful consideration in drain current compact modeling.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109105"},"PeriodicalIF":1.4,"publicationDate":"2025-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143725758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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