Solid-state Electronics最新文献

英文中文

Temperature influence on experimental analog behavior of MISHEMTs 温度对 MISHEMT 模拟实验行为的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-13 DOI: 10.1016/j.sse.2024.109028

Welder F. Perina , Joao A. Martino , Eddy Simoen , Uthayasankaran Peralagu , Nadine Collaert , Paula G.D. Agopian

This work presents an analysis on experimental analog behavior of MISHEMTs operating in the temperature range from 450 K down to 200 K. The drain current (I_DS) presented a slight anomaly, especially for temperatures lower than 400 K. In the transconductance it is possible to visualize a second peak, suggesting a second conduction. As shown, the transconductance presented a low dependence on gate length, and an anomaly was observed for the devices at 350 K. The output conductance and transistor efficiency behavior suggest a competition between the effects of the MOS and HEMT conductions, present in the device. A new kink was observed in the output characteristic (I_DSxV_DS) at room temperature, which is caused by the HEMT and MOS conductions interaction, and it is even more noticeable for higher overdrive voltages (V_GT). This effect is called MISHEMT kink effect (MH-kink) in this work. The MH-kink shifts toward higher V_DS for higher overdrive voltage, showing the stronger influence of the MOS conduction on the total drain current. The unity gain frequency (f_t) increases from 800 MHz (450 K) to 1.8 GHz (200 K), while the A_V goes in opposite direction from 43 dB (450 K) to 38 dB (200 K). Considering that the intrinsic voltage gain is good enough even at low temperatures, the MISHEMT can be identified as a good candidate for analog applications.

这项研究分析了在 450 K 至 200 K 温度范围内工作的 MISHEMT 的模拟实验行为。漏极电流（IDS）出现了轻微异常，尤其是在低于 400 K 的温度下。如图所示，跨导对栅极长度的依赖性较低，在 350 K 时器件出现异常。输出电导和晶体管效率行为表明，器件中存在 MOS 和 HEMT 传导效应之间的竞争。在室温下的输出特性（IDSxVDS）中观察到了一种新的扭结，这是 HEMT 和 MOS 导体相互作用造成的，在过驱动电压 (VGT) 较高时更为明显。这种效应在本文中称为 MISHEMT 扭结效应（MH-kink）。当过驱动电压升高时，MH-kink 会向更高的 VDS 方向移动，这表明 MOS 导通对漏极总电流的影响更大。统一增益频率 (ft) 从 800 MHz (450 K) 上升到 1.8 GHz (200 K)，而 AV 则相反，从 43 dB (450 K) 下降到 38 dB (200 K)。考虑到即使在低温条件下，MISHEMT 的固有电压增益也足够好，因此可以确定它是模拟应用的理想候选器件。

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引用次数: 0

A novel method used to prepare PN junction by plasmon generated under pulsed laser irradiation on silicon chip 利用脉冲激光照射硅芯片产生的等离子体制备 PN 结的新方法

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-08 DOI: 10.1016/j.sse.2024.109023

Wei-Qi Huang , Yin-Lian Li , Zhong-Mei Huang , Hao-Ze Wang , Shi-Rong Liu

We prepare the PN junction on silicon chip by a novel method with surface plasmon generated under pulsed laser irradiation. It is found that the interaction between laser photons and plasma produces a plasmon layer, in which the faster electrons take resonance with photons to generate surface electron gas. It is interesting that the electron gas in high vacuum and the plasmon polarized in various atmosphere are directly observed by the Talbot reflect image with outstanding challenge. It is demonstrated that injection and diffusion can be completed quickly to form higher quality PN region on interface between ions layer and substrate while the plasmon dipole makes resonance with phonon, where the quantum energy of plasmon is closed to the phonon energy in silicon crystal. In this novel way, the PN junction structure can be built by coherent photons on silicon chip at first, and the different preparing processes are explored comparatively by using the I-V curves measured with nonlinear characteristic of PN junction for application in optic-electronic integration field.

我们采用一种在脉冲激光照射下产生表面等离子体的新方法，在硅芯片上制备了 PN 结。研究发现，激光光子和等离子体之间的相互作用产生了等离子体层，其中速度较快的电子与光子发生共振，从而产生表面电子气。有趣的是，塔尔博特反射图像可以直接观测到高真空中的电子气和各种大气中的等离子体极化，具有很高的挑战性。实验证明，注入和扩散可以快速完成，从而在离子层和衬底之间的界面上形成更高质量的 PN 区域，同时等离子体偶极子与声子产生共振，而等离子体的量子能与硅晶体中的声子能接近。通过这种新颖的方法，相干光子可以在硅芯片上首先构建 PN 结结构，并利用测量到的 PN 结非线性特性的 I-V 曲线比较探讨了不同的制备过程，从而将其应用于光电子集成领域。

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引用次数: 0

Influence of Ag-Bi2S3 nanocomposites for highly sensitive and selective Cl2 gas sensors: Synthesis, characterization, and gas sensing performance Ag-Bi2S3 纳米复合材料对高灵敏度和选择性 Cl2 气体传感器的影响：合成、表征和气体传感性能

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-02 DOI: 10.1016/j.sse.2024.109024

Gangadhar Bandewad , Chetan Kamble , Sunil Pawar

The gas sensing capabilities of Bi₂S₃ chalcogenide have been actively enhanced and explored revealing its potential for high-performance Cl₂ gas detection under different environmental conditions and sensing configurations. This work successfully synthesized Bi₂S₃ material via the SILAR method and further enhanced its sensing capabilities by fabricating Ag-Bi₂S₃ nanocomposite. Both pristine Bi₂S₃ and Ag-Bi₂S₃ nanocomposite films underwent comprehensive characterization utilizing techniques such as FESEM, EDX, XRD, XPS, and RAMAN to analyze their morphological, structural, and chemical properties. Gas sensing capabilities were evaluated across a temperature range of 26–350 °C and varying Cl₂ gas concentrations (0.1–50 ppm). The findings reveal that the Ag-Bi₂S₃ sensor demonstrates notably superior Cl₂ sensing response, particularly at an operational temperature of 150 °C, suggesting its promising potential for Cl₂ detection. The LOD has been calculated for Ag-Bi₂S₃ sensor showing results of 0.150 better than pristine Bi₂S_3. HOMO-LUMO and PCA analysis for sensors has been studied to understand their capabilities with different gas sensing.

Bi2S3 Chalcogenide 的气体传感能力得到了积极的提升和探索，揭示了其在不同环境条件和传感配置下进行高性能 Cl2 气体检测的潜力。这项研究通过 SILAR 方法成功合成了 Bi2S3 材料，并通过制备 Ag-Bi2S3 纳米复合材料进一步增强了其传感能力。利用 FESEM、EDX、XRD、XPS 和 RAMAN 等技术对原始 Bi2S3 和 Ag-Bi2S3 纳米复合薄膜进行了全面表征，分析其形态、结构和化学特性。在 26-350 °C 的温度范围和不同的 Cl2 气体浓度（0.1-50 ppm）下，对其气体传感能力进行了评估。研究结果表明，Ag-Bi2S3 传感器的 Cl2 传感响应明显优于其他传感器，尤其是在 150 ℃ 的工作温度下，这表明它在 Cl2 检测方面具有很大的潜力。计算得出的 Ag-Bi2S3 传感器的 LOD 值比原始 Bi2S3 高 0.150。对传感器的 HOMO-LUMO 和 PCA 分析进行了研究，以了解它们对不同气体的传感能力。

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引用次数: 0

Achieving 15.75% efficiency in solar cells: Advanced surface engineering using Tetra-Tert-Butyl-Tercarbazol-Benzonitrile and organic layer integration in n-type silicon wafer and hybrid Planar-Si systems 实现 15.75% 的太阳能电池效率：使用四叔丁基三咔唑-苯腈的先进表面工程以及 n 型硅晶片和混合平面硅系统中的有机层集成

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-02 DOI: 10.1016/j.sse.2024.109025

Fahim Ullah , Kamran Hasrat , Sami Iqbal , Shuang Wang

This study investigates the progress in n-type solar cells utilizing implanted Tetra-Tert-Butyl-Tercarbazol-Benzonitrile (TTB-TB-BNZ) front surface fields and diffused Ag rear emitters. The n-type structure utilizes a systematic approach involving surface passivation, localized laser ablation, and screen printing, similar to commercial p-type solar cells. This design enables the conversion from p-type to n-type cell production. Ion implantation allows for accurate management of doping profiles, improving processing sequences and increasing efficiency. Analysis indicates that reduced post-implant annealing durations lead to a shallower doping profile, enhancing short-wavelength response. Its results in efficiencies reaching up to 15.75 % on large-area 200 cm2 n-type wafers. The study also examines hybrid planar-Si/organic heterojunction solar cells, emphasizing Tetra-Tert-Butyl-Tercarbazol-Benzonitrile (TTB-TB-BNZ) to improve photovoltaic efficiency. UV–visible and fluorescence spectroscopy indicate a maximum absorption wavelength of 360 nm and an emission wavelength of 420 nm. The concentration of TTB-TB-BNZ in (4,4′-di(9H-carbazol-9-yl)-1,1′-biphenyl) (CBP) films reaches its peak effectiveness at 40–50 %, leading to notable enhancements in light absorption and charge transport. The Si/PEDOT: PSS heterojunction solar cells incorporating TTB-TB-BNZ demonstrate a power conversion efficiency (PCE) of 15.75 %. This result underscores the potential for scalable fabrication methods to improve photovoltaic performance.

本研究探讨了利用植入式四叔丁基三咔唑-苯腈（TTB-TB-BNZ）前表面场和扩散式银后发射器的 n 型太阳能电池的研究进展。这种 n 型结构采用了与商用 p 型太阳能电池类似的系统方法，包括表面钝化、局部激光烧蚀和丝网印刷。这种设计实现了从 p 型电池到 n 型电池的生产转换。离子注入可实现对掺杂曲线的精确管理，改进加工顺序并提高效率。分析表明，缩短植入后退火持续时间可使掺杂剖面更浅，从而增强短波长响应。这使得 200 平方厘米大面积 n 型晶片的效率高达 15.75%。研究还考察了混合平面硅/有机异质结太阳能电池，强调利用四叔丁基三咔唑-苯腈（TTB-TB-BNZ）来提高光伏效率。紫外可见光谱和荧光光谱显示，其最大吸收波长为 360 纳米，发射波长为 420 纳米。在（4,4′-二（9H-咔唑-9-基）-1,1′-联苯）（CBP）薄膜中，TTB-TB-BNZ 的浓度在 40-50 % 时达到峰值效果，从而显著提高了光吸收和电荷传输能力。Si/PEDOT：PSS 异质结太阳能电池的功率转换效率 (PCE) 达到 15.75%。这一结果凸显了可扩展制造方法在提高光伏性能方面的潜力。

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引用次数: 0

Spiro-OMeTAD Anchoring perovskite for gradual homojunction in stable perovskite solar cells 在稳定的过氧化物太阳能电池中逐步实现同质结的螺氨过氧化物锚定过氧化物

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-01 DOI: 10.1016/j.sse.2024.109003

Ziyi Wang , Bobo Yuan , Yiheng Gao, Rui Wu, Shuping Xiao, Wuchen Xiang, Xueli Yu, Pingli Qin

The role of interface energetics-modification in interface-defect passivation and optimal interface energy-level matching is assumed to be a crucial aspect. Enhancing the performance and durability of perovskite solar cells (PSCs) can be achieved through this strategy. Here, spiro-OMeTAD [2,2′,7,7′-tetrakis (N, N-di-p-methoxyphenylamine)-9,9′-spirobifluorene] has been pipetted onto the spinning perovskite precursor film via a chlorobenzene anti-solvent strategy. It is found that spiro-OMeTAD serves as not only the filler at grain boundaries, but also the coverage on perovskite’s grain, and then forms the gradual homojunction interface from perovskite to spiro-OMeTAD hole transport layer, which can make spiro-OMeTAD anchor perovskite via the reaction between Pb²⁺ and C-O groups to decrease the interface barrier and obtain the optimal interface energy-level match between them for hole −migration and −collection. Moreover, these fillers or coverages can prevent moisture invading perovskite. Consequently, the counterpart PSC achieves a champion efficiency of 24.46 %, and has retained more than 88 % of the initial efficiency after 224 days of storage.

界面能量修饰在界面缺陷钝化和最佳界面能级匹配中的作用被认为是一个至关重要的方面。通过这种策略可以提高过氧化物太阳能电池（PSCs）的性能和耐用性。在这里，螺-OMeTAD [2,2′,7,7′-四（N,N-二对甲氧基苯胺）-9,9′-螺二芴] 通过氯苯反溶剂策略被吸附到旋转的过氧化物前驱体薄膜上。研究发现，螺-OMeTAD 不仅可以作为晶界的填充物，还可以覆盖在透辉石的晶粒上，进而形成透辉石与螺-OMeTAD 孔传输层的渐变同结界面，这可以使螺-OMeTAD 通过 Pb2+ 与 C-O 基团之间的反应锚定透辉石，从而降低界面势垒，使二者之间获得最佳的界面能级匹配，以实现孔的迁移和收集。此外，这些填充物或覆盖物还能防止水分侵入包晶。因此，对应的 PSC 实现了 24.46% 的冠军效率，并在储存 224 天后保持了超过 88% 的初始效率。

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引用次数: 0

Silicon-based integrated passive device stack for III-V/Si monolithic 3D circuits operating on RF band 用于射频波段 III-V/Si 单片 3D 电路的硅基集成无源器件堆栈

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-10-22 DOI: 10.1016/j.sse.2024.109012

Minsik Park , Minkyoung Seong , Jaeyong Jeong , Seungin Lee , Jonghyun Song , Hyoungho Ko , Ga-Won Lee , Woo-Suk Sul , Won-Chul Lee , Sanghyeon Kim , Jongwon Lee

In this study, we demonstrated a silicon (Si)-based integrated passive device (IPD) stack to support III-V/Si monolithic 3D (M3D) ICs operating on the radio frequency (RF) band. The IPD stack was fabricated based on an 8-inch CMOS process line and integrated via M3D with an InGaAs HEMT layer. A process condition for a trap rich layer and a buried oxide layer in the IPD was established to simultaneously minimizing both the RF loss and wafer bowing. Through the process condition, the RF loss of the coplanar waveguides was −0.631 dB/mm at 30 GHz, lower than that of the CMOS foundry, and the wafer bowing of the stack was as low as −5.5 μm. The maximum quality factor of the inductors showed good values when compared to those of other CMOS foundry process-based inductors operating on the RF bands reported thus far. To obtain a compressive profile for the IPD stack, which is one of the most important requirements in advancing to wafer-to-wafer-level 3D bonding with the III-V active layer, a process method for the final IMD layer of the IPD was developed, resulting in a change from a tensile profile to a compressive profile for the IPD (corresponding wafer bowing value from −12.6 to + 10.7 μm).

在这项研究中，我们展示了一种基于硅（Si）的集成无源器件（IPD）堆栈，用于支持在射频（RF）频段工作的 III-V/Si 单片 3D (M3D) 集成电路。该 IPD 堆栈基于 8 英寸 CMOS 工艺线制造，并通过 M3D 与 InGaAs HEMT 层集成。为了同时最大限度地降低射频损耗和晶圆弯曲，在 IPD 中建立了富阱层和埋入氧化层的工艺条件。通过该工艺条件，共面波导在 30 GHz 时的射频损耗为 -0.631 dB/mm，低于 CMOS 代工厂的水平，而叠层的晶圆弯曲则低至 -5.5 μm。与迄今报道的在射频频段工作的其他基于 CMOS 代工工艺的电感器相比，电感器的最大品质因数显示出良好的数值。为了获得 IPD 叠层的压缩轮廓（这是将 III-V 有源层推进到晶圆到晶圆级 3D 粘合的最重要要求之一），开发了一种用于 IPD 最后 IMD 层的工艺方法，从而使 IPD 从拉伸轮廓变为压缩轮廓（相应的晶圆弯曲值从 -12.6 μm 到 +10.7 μm）。

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引用次数: 0

Influence of gate work function variations on characteristics of fin-shaped silicon quantum dot device with multi-gate under existence of gate electrostatic coupling 栅极功函数变化对存在栅极静电耦合的多栅极鳍状硅量子点器件特性的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-10-22 DOI: 10.1016/j.sse.2024.109013

Kimihiko Kato, Hidehiro Asai, Hiroshi Oka, Shota Iizuka, Hiroshi Fuketa, Takumi Inaba, Takahiro Mori

We explored the effects of gate work function variation (WFV) through device simulation on a fin-shaped silicon quantum dot device with a multi-gate configuration for a large-scale integrated array. The threshold voltage (V_th) of current–voltage characteristics is affected by WFV in both main and surrounding gates, indicating the existence of electrostatic coupling among these gates. The electrostatic coupling can be reduced by biasing on the surrounding gates. Furthermore, the concept of V_th, following conventional transistors, works as a reference of voltage and potential in the present multi-gate device. This knowledge contributes to establishing a practical method for the statistical analysis of qubit variability.

我们通过对大规模集成阵列多栅极配置的鳍状硅量子点器件进行器件仿真，探索了栅极功函数变化（WFV）的影响。电流-电压特性的阈值电压（Vth）受主栅极和周围栅极的 WFV 影响，表明这些栅极之间存在静电耦合。通过对周围栅极进行偏压，可以降低静电耦合。此外，Vth 的概念沿袭了传统晶体管，在目前的多栅极器件中可作为电压和电势的参考。这些知识有助于为量子位变异性统计分析建立一种实用方法。

引用次数: 0

Sputter-Deposited copper iodide thin film transistors with low Operating voltage 低工作电压的溅射沉积碘化铜薄膜晶体管

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-10-21 DOI: 10.1016/j.sse.2024.109014

Zachary C. Adamson , Rotem Zilberberg , Iryna Polishchuk , Natalia Thomas , Kyumin Kim , Alexander Katsman , Boaz Pokroy , Alexander Zaslavsky , David C. Paine

This paper reports on a back-gated p-type thin film transistor (TFT) with copper iodide (CuI) as the channel material, a HfO₂ gate dielectric layer, and Al₂O₃ passivation. The γ-CuI channel was deposited from a CuI target using DC magnetron sputtering at room temperature. Our TFT can be fully shut off by V_G = 4 V, with a field-effect channel hole mobility μ_h ∼ 1.5–2 cm² V⁻¹ s⁻¹. An anneal in forming gas was performed twice, once at 200 °C, then at 250 °C to improve gate control, yielding a final I_on/I_off current ratio of ∼ 250. The anneal served two purposes: to reduce the oxygen acceptor density in the CuI channel and reduce the concentration of interface states between the CuI, Al₂O₃ passivation, and HfO₂. A model of the device was built in an industrial TCAD simulator, which reproduces the measured characteristics and allows an estimation of interface state densities and channel doping.

本文报告了一种以碘化铜（CuI）为沟道材料、HfO2 栅极电介质层和 Al2O3 钝化层的背栅 p 型薄膜晶体管（TFT）。γ-CuI沟道是在室温下利用直流磁控溅射技术从CuI靶上沉积下来的。我们的 TFT 可以在 VG = 4 V 时完全关闭，其场效应沟道空穴迁移率 μh ∼ 1.5-2 cm2 V-1 s-1。在成型气体中进行了两次退火，一次是在 200 ℃，另一次是在 250 ℃，以改善栅极控制，最终离子/关断电流比为 ∼ 250。退火有两个目的：降低 CuI 沟道中的氧受体密度；降低 CuI、Al2O3 钝化层和 HfO2 之间的界面态浓度。在工业 TCAD 模拟器中建立了该器件的模型，该模型再现了测量到的特性，并允许对界面态密度和沟道掺杂进行估计。

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引用次数: 0

Enhanced resistive switching performance in TiN/AlOx/Pt RRAM by high-temperature I-V cycling 通过高温 I-V 循环提高 TiN/AlOx/Pt RRAM 的电阻开关性能

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-10-15 DOI: 10.1016/j.sse.2024.109011

Tao He , Huiyu Yan , Yixuan Wang

Set voltage is a key parameter for the application of Resistance Random Access Memory (RRAM). In this paper, based on TiN/AlO_x/Pt RRAM synthesized by the magnetron sputtering method, we have studied the influence of I-V cycling at high temperatures on resistive switching performance. The results show that the treatment can significantly reduce the set voltage in resistive switching cycles. Moreover, the treatment can also enhance endurance effectively. Further studies indicated that a higher compliance current in treatment can induce a smaller and more uniform set voltage. We ascribe the improvements in resistive switching performance to the generation and accumulation of oxygen vacancies in the treatment. This research provides new ideas for synthesizing RRAM devices with low power consumption.

设定电压是电阻随机存取存储器（RRAM）应用的一个关键参数。本文以磁控溅射法合成的 TiN/AlOx/Pt RRAM 为基础，研究了高温下 I-V 循环对电阻开关性能的影响。结果表明，这种处理方法可以显著降低电阻开关循环中的设定电压。此外，这种处理方法还能有效提高耐久性。进一步的研究表明，处理过程中的顺应电流越大，设定电压就越小、越均匀。我们将电阻开关性能的改善归因于处理过程中氧空位的产生和积累。这项研究为合成低功耗 RRAM 器件提供了新思路。

引用次数: 0

A well-conditioned surface potential equation for dynamically depleted SOI MOS devices accounting for the front-depletion/back-accumulation operation mode 适用于动态耗尽型 SOI MOS 器件的表面电势方程（考虑了前耗尽/后积累工作模式

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-10-10 DOI: 10.1016/j.sse.2024.109010

Thomas Bédécarrats, Sébastien Martinie, Adrien Vaysset, Olivier Rozeau

This paper provides an improved surface potential equation for compact modeling of dynamically depleted silicon-on-insulator MOS device. It removes the non-physical front-gate capacitance prediction and the discontinuity at the flat-band condition present in previous works. It also includes for the first time the back gate effect observed at negative back gate voltage when the silicon film is partially depleted. It relies on, firstly, an approximated description of the front-depletion/back-accumulation mode of operation that has always been ignored by now, and secondly, an appropriate mathematical conditioning. The model is validated by 3D TCAD simulations.

本文为动态耗尽型硅绝缘体 MOS 器件的紧凑建模提供了一种改进的表面电势方程。它消除了之前工作中存在的非物理前栅极电容预测和平带条件下的不连续性。它还首次包含了硅薄膜部分耗尽时在负后栅电压下观察到的后栅效应。首先，它依赖于对迄今为止一直被忽视的前耗尽/后累积工作模式的近似描述；其次，它依赖于适当的数学条件。三维 TCAD 仿真验证了该模型。

引用次数: 0

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