Solid-state Electronics最新文献

Short-term charge trapping effects in ferroelectric FETs: impact of pulse amplitude and timing 铁电场效应管中的短期电荷俘获效应：脉冲振幅和时序的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-01-11 DOI: 10.1016/j.sse.2026.109332

Dominik Kleimaier , Stefan Dünkel , Halid Mulaosmanovic , Johannes Müller , Sven Beyer , Viktor Havel , Thomas Mikolajick

This study investigates the short-term (µs to s timespan) charge trapping effects in hafnium oxide-based ferroelectric field-effect transistors, integrated within GlobalFoundries’ 28 nm bulk high-k metal gate (HKMG) technology.

Even without ferroelectric switching, positive gate voltage pulses can cause significant short-term electron trapping due to strong energy band bending that enables charge injection.

A systematic analysis reveals that the extent of short-term trapping increases with both the amplitude and the duration of the applied gate pulses. These dependencies are consolidated into a positive bias charge trapping matrix, offering an overview of how various factors collectively influence trapping behavior. Negative gate bias does not cause charge trapping in FeFETs for the investigated voltage and time domain.

Building on previous reports of degradation-free unipolar endurance cycling, these observations further support the conclusion that the pronounced short-term trapping effects are primarily non-destructive.

The study highlights the importance of understanding and accounting for short-term charge trapping effects, especially as they relate to read-after-write capabilities and overlaps with switching mechanisms. This understanding is crucial for optimizing the consistent and effective operation of FeFETs as memory cells and neuromorphic computing elements.

本研究研究了基于氧化铪的铁电场效应晶体管的短期（µs到s时间范围）电荷捕获效应，该晶体管集成在GlobalFoundries的28nm大块高k金属栅极（HKMG）技术中。即使没有铁电开关，正栅极电压脉冲也会由于强能带弯曲导致电荷注入而导致显著的短期电子捕获。系统的分析表明，短期捕获的程度随着施加的门脉冲的幅度和持续时间的增加而增加。这些依赖关系被整合到一个正偏压电荷捕获矩阵中，提供了各种因素如何共同影响捕获行为的概述。负栅极偏置在所研究的电压和时域中不会引起场效应管中的电荷捕获。基于先前关于无降解单极耐力循环的报告，这些观察结果进一步支持了短期捕获效应主要是非破坏性的结论。该研究强调了理解和考虑短期电荷捕获效应的重要性，特别是当它们与写后读能力和开关机制重叠时。这种理解对于优化效应场效应管作为记忆细胞和神经形态计算元件的一致和有效运作至关重要。

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引用次数: 0

Impact of top electrode materials on resistive switching characteristics of TiOx-based MIM structures 顶电极材料对tiox基MIM结构阻性开关特性的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-01-01 DOI: 10.1016/j.sse.2025.109329

Karimul Islam , Rezwana Sultana , Aleksandra Dzięgielewska , Robert Mroczyński

This study investigates the influence of the top metal electrode on the resistive switching (RS) behavior of the metal/TiO_x/ITO structure. Specifically, the effects of Al and TiN as top electrodes were examined in devices utilizing a 30 nm TiO_x thin film as the active layer, deposited using a pulsed-DC reactive sputtering technique. Both configurations exhibited non-volatile bipolar resistive switching, demonstrating endurance over 100 cycles and stable data retention (>10⁴ s). The results indicate that the choice of top electrode (TE) plays a crucial role in determining the electroforming process, current conduction mechanisms, and overall RS performance. Notably, devices with TiN as a TE exhibited more consistent RS behavior, with a superior ON/OFF ratio and enhanced operational stability. These findings demonstrate that electrode engineering offers a viable pathway to enhance resistive switching performance. The insights gained from this study provide a basis for the rational design and optimization of CMOS-compatible TiO_x-based resistive random-access memory (RRAM) devices.

本文研究了顶部金属电极对金属/TiOx/ITO结构电阻性开关（RS）行为的影响。具体来说，使用脉冲直流反应溅射技术沉积的30 nm TiOx薄膜作为活性层，在器件中测试了Al和TiN作为顶电极的效果。这两种配置都具有非易失性双极电阻开关，具有超过100次循环的耐久性和稳定的数据保留（104秒）。结果表明，顶电极（TE）的选择对电铸工艺、电流传导机制和整体RS性能起着至关重要的作用。值得注意的是，以TiN为TE的器件表现出更一致的RS行为，具有优越的开/关比和增强的工作稳定性。这些发现表明，电极工程为提高电阻开关性能提供了一条可行的途径。本研究为合理设计和优化cmos兼容的tiox型电阻随机存取存储器（RRAM）器件提供了基础。

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引用次数: 0

Application of forksheet transistor in operational transconductance amplifier 叉片晶体管在运算跨导放大器中的应用

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-01-01 DOI: 10.1016/j.sse.2025.109330

Joao Antonio Martino , Julius Andretti Peixoto Pires de Paula , Paula Ghedini Der Agopian , Romain Ritzenthaler , Hans Mertens , Anabela Veloso , Naoto Horiguchi

This work presents, for the first time, experimental data on forksheet transistor used in the design of operational transconductance amplifiers (OTA), highlighting their potential for application in analog circuits. The OTA was designed for three different transistor efficiencies: gm/I_D of 5, 8 and 11 V⁻¹. The experimental n-type forksheet used in this work presents a sheet thickness of H_FS = 7 nm, sheet width of W_FS = 23 nm and a transistor channel length of L_G = 70 nm. When the gm/I_D increases from 5 to 11 V⁻¹, the drain current and the transconductance decrease, which improves the OTA voltage gain (Av ∝ gm/I_D) from 49 dB to 63 dB, the total power dissipation (Power ∝ I_D) also improves (decreases) from 528 μW to 129 μW, while degrades the Gain-Bandwidth Product (GBW) from 343 MHz to 196 MHz (GBW ∝ gm). Depending on the application, the OTA bias conditions must be set appropriately due to the trade-off between Av and GBW. The obtained results show that the forksheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits using this technology.

这项工作首次展示了用于操作跨导放大器（OTA）设计的叉片晶体管的实验数据，突出了它们在模拟电路中的应用潜力。OTA设计用于三种不同的晶体管效率：gm/ID为5、8和11 V−1。本实验采用的n型叉片，片厚HFS = 7 nm，片宽WFS = 23 nm，晶体管通道长度LG = 70 nm。当gm/ID从5 V−1增加到11 V−1时，漏极电流和跨导减小，使OTA电压增益（Av∝gm/ID）从49 dB提高到63 dB，总功耗（power∝ID）也从528 μW提高（降低）到129 μW，增益带宽积（GBW）从343 MHz降低到196 MHz （GBW∝gm）。根据不同的应用，由于Av和GBW之间的权衡，必须适当设置OTA偏置条件。结果表明，该叉片可用于OTA等模拟电路，可应用于混合信号集成电路中。

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引用次数: 0

Radio-frequency variability of GAA Si NS CFETs induced by PVE and IPF simultaneously PVE和IPF同时诱导GAA Si NS cfet的射频变异性

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-30 DOI: 10.1016/j.sse.2025.109326

Sekhar Reddy Kola , Min-Hui Chuang , Yiming Li

Variability in gate-all-around (GAA) silicon nanosheet (Si NS) complementary field-effect transistors (CFETs) stems from two primary sources: process-variation effect (PVE) and intrinsic parameter fluctuations (IPF). In this work, a systematic TCAD-based variability framework is developed to quantitatively assess the impact of PVE and IPF on the analog and radio frequency (RF) performance of vertically stacked GAA Si NS CFETs. Key geometrical factors—namely NS thickness (T_NS), width (W_NS), and gate length (L_G)—play a pivotal role in shaping intrinsic resistance (r_o), output resistance (R_out), voltage gain (A_V), cut-off frequency (f_T), and 3-dB bandwidth (f₃_dB), due to their influence on surface potential profiles and carrier transport behavior. Notably, within IPF, variations are predominantly governed by random nanoscale metal grains, where work function fluctuations (WKF) strongly perturb the channel surface potential, thereby inducing significant variability in A_V, f_T, f₃_dB, other radio RF parameters. A statistically significant ensemble of calibrated device simulations is employed to decouple and quantify the individual and combined contributions of PVE and IPF. Furthermore, small-signal s-parameter analysis is performed to extract RF figures of merit under realistic loading conditions, providing practical design insights for variability-aware CFET optimizations.

栅极全能（GAA）硅纳米片互补场效应晶体管（cfet）的可变性主要来自两个方面：工艺变化效应（PVE）和内在参数波动（IPF）。在这项工作中，开发了一个系统的基于tcad的可变性框架，以定量评估PVE和IPF对垂直堆叠GAA Si NS cfet模拟和射频（RF）性能的影响。关键的几何因素-即NS厚度（TNS），宽度（WNS）和栅极长度(LG) -由于其对表面电位分布和载流子输运行为的影响，在形成固有电阻（ro），输出电阻（route），电压增益（AV），截止频率（fT）和3db带宽（f3dB）中起关键作用。值得注意的是，在IPF中，变化主要由随机纳米级金属颗粒控制，其中功函数波动（WKF）强烈干扰通道表面电位，从而诱导AV、fT、f3dB和其他射频参数的显著变化。采用统计上显著的校准设备模拟集合来解耦和量化PVE和IPF的单独和联合贡献。此外，还进行了小信号s参数分析，以提取实际负载条件下的RF值，为可变感知的CFET优化提供实用的设计见解。

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引用次数: 0

Warm white electrical sensitivities of pentacene-based Schottky photodiode 五苯基肖特基光电二极管的暖白色电灵敏度

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-29 DOI: 10.1016/j.sse.2025.109327

Ghusoon M. Ali , Kahtan Adnan Hussain , Shahad T. Armoot

This study investigates the electrical sensitivities of warm white Al/pentacene/p-Si/Pd Schottky photodiodes with respect to current–voltage (I-V), capacitance–voltage (C-V), and conductance-voltage (G-V) characteristics. The pentacene thin film is deposited using the vacuum thermal evaporation technique. The energy level parameters of the Schottky junction are estimated through energy band diagrams. Two models are introduced to analyze the forward I-V characteristics of the pentacene Schottky diode: the thermionic emission theory and the space-charge-limited current model, both of which explain the mechanisms of charge carrier transport. The I-V, C-V, and G-V characteristics were examined under both dark and warm white illumination conditions, across a voltage range of −4 to 4 V at room temperature. Moreover, a study was conducted to assess, extract, and compare the sensitivities of current (S_I), capacitance (S_C), and conductance (S_CO). The maximum S_I is 1682 % at 0 V. Therefore, the proposed device demonstrates outstanding performance as a self-powered photodetector. The maximum S_C is 38 % at −2.1 V, and S_CO is 370 % at −1.6 V. The variations in sensitivity values are attributed to the different detection mechanisms employed. Overall, the results demonstrate the significant potential of the current-mode Schottky pentacene diode for use as a warm white self-powered photodetector.

本研究考察了暖白色Al/pentacene/p-Si/Pd肖特基光电二极管在电流电压（I-V）、电容电压（C-V）和电导电压（G-V）特性方面的电灵敏度。采用真空热蒸发技术制备了并五苯薄膜。利用能带图估计了肖特基结的能级参数。引入了热离子发射理论和空间电荷限制电流模型两种模型来分析并苯肖特基二极管的正向I-V特性，这两种模型都解释了载流子输运的机理。在室温下，在−4到4 V的电压范围内，在黑暗和温暖的白色照明条件下，研究了I-V、C-V和G-V特性。此外，还进行了一项研究，以评估、提取和比较电流（SI）、电容（SC）和电导（SCO）的灵敏度。在0 V时，最大SI为1682 %。因此，所提出的器件表现出作为自供电光电探测器的出色性能。在−2.1 V时最大SC为38 %，在−1.6 V时最大SCO为370 %。灵敏度值的变化归因于所采用的不同检测机制。总的来说，结果证明了电流模式肖特基五苯二极管作为暖白色自供电光电探测器的巨大潜力。

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引用次数: 0

Geometrical and thermal effects on mobility and analog parameters of AlGaN/GaN HEMTs on silicon substrates 几何和热效应对硅衬底上AlGaN/GaN hemt迁移率和模拟参数的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-20 DOI: 10.1016/j.sse.2025.109316

Maria Glória Caño de Andrade , Braz Baptista Júnior , Eduardo Canga Panzo , Rodrigo T. Doria , Renan Trevisoli , Eddy Simoen

This work investigates how temperature and channel geometry affect the analog performance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on silicon. Devices with varying lengths and widths were characterized across a temperature range from −35 °C to 25 °C. Four different methods were used to extract the carrier mobility: effective mobility (μ_eff) calculated from the ratio I_D/(V_G–V_T) at low drain voltage; field-effect mobility (μ_FE) obtained from the transconductance in the linear regime; low-field mobility (μ_o) estimated from the drift–diffusion model; and peak transconductance mobility derived from the maximum value of g_m. The results consistently followed the trend μ_eff > μ_FE > μ_o, and all mobilities showed degradation with increasing temperature due to enhanced phonon scattering. Key parameters such as threshold voltage (V_T), subthreshold swing (SS), transconductance (g_m), DIBL, output conductance (g_D), Early voltage (V_EA), and intrinsic gain (A_V) were also evaluated, confirming that temperature and geometry critically influence device performance.

本研究探讨了温度和沟道几何形状如何影响在硅上制造的AlGaN/GaN高电子迁移率晶体管（hemt）的模拟性能。具有不同长度和宽度的器件在−35°C至25°C的温度范围内进行表征。采用四种不同的方法提取载流子迁移率：低漏极电压下由ID/(VG-VT)计算有效迁移率（μeff）；由线性区跨导得到的场效应迁移率μFE；漂移扩散模型估计的低场迁移率μo；结果一致符合μeff >； μFE >； μo的趋势，并且由于声子散射增强，所有的迁移率都随着温度的升高而降低。还评估了阈值电压（VT）、亚阈值摆幅（SS）、跨导（gm）、DIBL、输出电导（gD）、早期电压（VEA）和固有增益（AV）等关键参数，确认温度和几何形状对器件性能有重要影响。

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引用次数: 0

1T-DRAM with retrograde doping 逆行掺杂的t - dram

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-18 DOI: 10.1016/j.sse.2025.109315

Maki Ulla , MD Yasir Bashir , Mohammad Jawaid Siddiqui

This work presents a 1T-DRAM design based on a double-gate junctionless (DGJL) transistor with retrograde doping (RD), aimed at improving charge storage and scaling. The retrograde doping profile changes the carrier distribution in the channel, creating a strong electric field gradient near the drain when voltage is applied. This strong electric field causes sharp band bending, which reduces the tunneling barrier width and increases lateral band-to-band tunneling (L-BTBT) gate-induced drain leakage (GIDL) current. As a result, efficient holes generated in the channel at lower write voltages with a retention time of up to 80 ms at ultra short gate length of 20 nm. The proposed DGJL RD-based 1T-DRAM is analyzed using well calibrated 2D TCAD simulation. Furthermore, the effects of work function, gate length, temperature, and doping level on retention time and sense margin are also studied, showing the potential of this design for low-power and highly scalable memory applications.

这项工作提出了一种基于双栅无结（DGJL）晶体管和逆行掺杂（RD）的1T-DRAM设计，旨在改善电荷存储和缩放。逆行掺杂剖面改变了沟道中的载流子分布，当施加电压时在漏极附近产生强电场梯度。这种强电场导致了剧烈的能带弯曲，从而减小了隧道势垒宽度，增加了横向带对带隧道（L-BTBT）栅极诱发漏极（GIDL）电流。结果，在较低的写入电压下，沟道中产生了有效的空穴，在20nm的超短栅极长度下，保留时间高达80ms。采用校准良好的二维TCAD仿真分析了DGJL RD-based 1T-DRAM。此外，还研究了功函数、栅极长度、温度和掺杂水平对保留时间和感测余量的影响，显示了该设计在低功耗和高可扩展存储应用中的潜力。

引用次数: 0

Unified approach for considering the effect of doping and device temperature on the band structure and electrostatics of UTB SOI DG MOS devices 考虑掺杂和器件温度对UTB SOI DG MOS器件能带结构和静电影响的统一方法

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-09 DOI: 10.1016/j.sse.2025.109313

Yogesh Dhote, Nalin Vilochan Mishra, Aditya Sankar Medury

In this work, we present a tight-binding method (TBM) based algorithm to consider the effects of channel doping on the band structure and the band gap of an Ultra-Thin Body (UTB) Double Gate (DG) Silicon-on-Insulator (SOI) MOS device, through the inclusion of doping dependent self energy correction terms in the tight-binding (TB) Hamiltonian. Firstly, we use the existing Band gap Narrowing (BGN) models as a reference and determine the self-energy correction terms to be included in the Tight-Binding Hamiltonian of a thick and intrinsic SOI channel (43 nm, where quantum confinement effects are negligible) at room temperature, to ensure that the effects of n and p type doping can be accurately taken into account. By using the same self-energy correction terms, while also now including a temperature dependent band gap correction, we then quantify the extent of band gap narrowing for a wide range of device temperatures (15 K - 300 K), channel thicknesses and doping densities. We further evaluate the channel electrostatics of these devices through the self-consistent solution of the band structure with the Poisson’s equation. Also by using the band structure based simulation approach, we then propose a model for the band gap considering channel doping, thickness and device temperature variations.

在这项工作中，我们提出了一种基于紧密结合方法（TBM）的算法，通过在紧密结合（TB）哈密顿量中包含与掺杂相关的自能校正项，来考虑通道掺杂对超薄体（UTB）双栅（DG）绝缘体上硅（SOI） MOS器件的能带结构和带隙的影响。首先，我们以现有的带隙缩小（BGN）模型为参考，确定室温下厚度和本征SOI通道（43 nm，量子约束效应可以忽略）的紧密结合哈密顿量中包含的自能量修正项，以确保n和p型掺杂的影响可以准确考虑。通过使用相同的自能校正项，同时也包括温度相关的带隙校正，然后我们量化了在大范围的器件温度（15 K - 300 K）、沟道厚度和掺杂密度下带隙缩小的程度。通过用泊松方程求解带结构的自洽解，进一步评价了这些器件的通道静电特性。此外，通过基于带结构的仿真方法，我们提出了考虑通道掺杂、厚度和器件温度变化的带隙模型。

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引用次数: 0

Improving the analog switching behavior in HfO2-based RRAM with simple 1T1R structure configuration 用简单的1T1R结构改善基于hfo2的RRAM的模拟开关行为

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-08 DOI: 10.1016/j.sse.2025.109314

Jian Xia , Huikai He , Dingyi Shen , Xiangyang Jiang , Juntao Yang

Resistive random-access memory (RRAM) featuring analog switching (AS) presents a compelling prospect for computing-in-memory (CIM) applications. However, achieving desirable analog switching behavior in filamentary RRAM cells remains challenging. In this work, two device structure configurations (1nT1rR & 1pT1R) were proposed to improve the AS behavior in one transistor and one resistor (1T1R) structure RRAM. The effect of the device structure configuration on analog switching behavior in 1T1R RRAM is elucidated. Compared with the conventional configuration in 1T1R RRAM, the RRAM with 1nT1rR & 1pT1R structure can effectively solve the problem of an abrupt changes in conductivity caused by the self-acceleration of ion migration during SET process. Under the excitation of electrical signals, the device shows excellent analog switching behavior and can achieve continuous modulation of conductivity. Thanks to the good linearity of the conductance modulation in the RRAM with modified structure, an artificial neural network (ANN) is established for the task of handwritten digit images recognition with a recognition accuracy of over 91%. Our work provides a simple strategy for the optimization of the switching behavior in RRAM and demonstrates great potential in the field of neuromorphic computing.

以模拟开关（AS）为特征的电阻式随机存取存储器（RRAM）在内存计算（CIM）应用中具有引人注目的前景。然而，在丝状RRAM单元中实现理想的模拟开关行为仍然具有挑战性。在这项工作中，提出了两种器件结构配置（1nT1rR & 1pT1R）来改善一个晶体管和一个电阻（1T1R）结构RRAM的AS行为。阐明了器件结构对1T1R RRAM中模拟开关行为的影响。与传统的1T1R RRAM结构相比，采用1nT1rR &； 1pT1R结构的RRAM可以有效地解决SET过程中离子迁移自加速导致电导率突变的问题。在电信号的激励下，该器件表现出优异的模拟开关性能，并能实现电导率的连续调制。利用改进结构的RRAM中电导调制的良好线性度，建立了一种人工神经网络（ANN）来完成手写数字图像的识别任务，识别准确率超过91%。我们的工作为优化RRAM中的开关行为提供了一种简单的策略，并在神经形态计算领域展示了巨大的潜力。

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引用次数: 0

A 10T2R non-volatile SRAM cell design with high-reliability 一种高可靠性的10T2R非易失性SRAM单元设计

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-05 DOI: 10.1016/j.sse.2025.109304

So-Yeon Kwon, Woon-San Ko, Jun-Ho Byun, Do-Yeon Lee, So-Yeong Park, Hye-Ri Hong, Ga-Won Lee

In this study, a highly reliable 10T2R non-volatile SRAM (nvSRAM) cell is proposed. The previous nvSRAM structures face reliability issues of Resistive Random-Access Memory (RRAM) due to unwanted stress-induced data nodes. To overcome this challenge, the proposed 10T2R nvSRAM design integrates two transistors that effectively isolate both ends of the RRAM, acting as voltage blockers and current controllers. The SPICE simulation results show that the voltage stress applied to the RRAM during the Read/Write operation is less than 1 mV. Regarding the static noise margin (SNM), the SNM value of the 10T2R in each operation is similar to that of a 6T SRAM. Additionally, it successfully performs the RESTORE operation after power-on and demonstrates low power consumption. This highlights the potential of the proposed 10T2R cell to advance non-volatile memory technology.

在这项研究中，提出了一个高可靠的10T2R非易失性SRAM （nvSRAM）单元。以前的nvSRAM结构由于不需要应力引起的数据节点而面临电阻随机存取存储器（RRAM）的可靠性问题。为了克服这一挑战，提出的10T2R nvSRAM设计集成了两个晶体管，有效地隔离了RRAM的两端，作为电压阻滞器和电流控制器。SPICE仿真结果表明，读写过程中施加在RRAM上的电压应力小于1 mV。关于静态噪声裕度（SNM）， 10T2R在每次操作中的SNM值与6T SRAM相似。开机后能成功执行RESTORE操作，功耗低。这突出了所提出的10T2R电池在推进非易失性存储技术方面的潜力。

引用次数: 0