Solid-state Electronics最新文献

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Expanding the potential of Zn0.15Sn0.85(Se0.95S0.05)2 crystals for applications in near-infrared optoelectronics, sensing, and Van der Waals heterojunctions

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-03-15 DOI: 10.1016/j.sse.2025.109104

Yash N. Doshi , Dixita S. Parmar , Ajay D. Zanpadiya , Aditi P. Pathak , Divya R. Solanki , Dimple V. Shah , Vishva M. Jain , Hiren N. Desai , Piyush B. Patel

Layered Zn_0.15Sn_0.85(Se_0.95S_0.05)₂ (Q2) crystals with a hexagonal crystalline structure were grown using the direct vapor transport technique (DVT). This research explores applications of the grown Q2 crystals as a near-infrared (NIR) photodetector, vacuum pressure sensor, and Van der Waals heterojunction. The NIR photodetector demonstrating stable, rapid switching with an improved responsivity of 153.38 mAW^-1. A Q2 crystal-based NIR photodetector achieves an external quantum efficiency of 21.17 %. The Maxwellian distribution was applied to analysis trap depth of NIR photodetector. Additionally, the pulse resistive response of the Q2 crystal-based vacuum pressure sensor was evaluated across a vacuum pressure range from −1033 mbar to 0 mbar. The sensor exhibited a stable response, with 61.27 % at −1033 mbar and 5.85 % at −133 mbar with an average delay time of 2.99 s. Furthermore, the Van der Waals heterojunction device formed by the grown p-type Q2 crystals with another n-type quaternary crystal was studied using the thermionic-emission (TE) model. The ideality factors have been defined in the range of 1 to 2 by studying the current voltage (I-V) characteristics under different temperatures.

{"title":"Expanding the potential of Zn0.15Sn0.85(Se0.95S0.05)2 crystals for applications in near-infrared optoelectronics, sensing, and Van der Waals heterojunctions","authors":"Yash N. Doshi , Dixita S. Parmar , Ajay D. Zanpadiya , Aditi P. Pathak , Divya R. Solanki , Dimple V. Shah , Vishva M. Jain , Hiren N. Desai , Piyush B. Patel","doi":"10.1016/j.sse.2025.109104","DOIUrl":"10.1016/j.sse.2025.109104","url":null,"abstract":"<div><div>Layered Zn<sub>0.15</sub>Sn<sub>0.85</sub>(Se<sub>0.95</sub>S<sub>0.05</sub>)<sub>2</sub> (Q2) crystals with a hexagonal crystalline structure were grown using the direct vapor transport technique (DVT). This research explores applications of the grown Q2 crystals as a near-infrared (NIR) photodetector, vacuum pressure sensor, and Van der Waals heterojunction. The NIR photodetector demonstrating stable, rapid switching with an improved responsivity of 153.38 mAW<sup>-1</sup>. A Q2 crystal-based NIR photodetector achieves an external quantum efficiency of 21.17 %. The Maxwellian distribution was applied to analysis trap depth of NIR photodetector. Additionally, the pulse resistive response of the Q2 crystal-based vacuum pressure sensor was evaluated across a vacuum pressure range from −1033 mbar to 0 mbar. The sensor exhibited a stable response, with 61.27 % at −1033 mbar and 5.85 % at −133 mbar with an average delay time of 2.99 s. Furthermore, the Van der Waals heterojunction device formed by the grown p-type Q2 crystals with another n-type quaternary crystal was studied using the thermionic-emission (TE) model. The ideality factors have been defined in the range of 1 to 2 by studying the current voltage (I-V) characteristics under different temperatures.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109104"},"PeriodicalIF":1.4,"publicationDate":"2025-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143642555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Intense near-infrared electroluminescence properties from ZnO:Yb LED

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-03-12 DOI: 10.1016/j.sse.2025.109102

Qingxue Zhao , Shenwei Wang , Zhengmao Wen , Weifang Zhang , Xiaoxia Duan , Lixin Yi

Rare-earth (RE) doped zinc oxide electroluminescence is worthy of study due to its pure and sharp luminescence characteristics. In this work, we report ZnO:Yb light-emitting diodes (LED) and test their electroluminescence properties. Through adjusting the concentration of ytterbium doping and optimizing of annealing parameters for ZnO:Yb thin films, the results show that ZnO:Yb light-emitting diodes are capable of generating intense near-infrared emission at 975 nm and 1004 nm. We contend that impact excitation is the predominant mechanism underlying the electroluminescence in ITO/PEDOT:PSS/ZnO:Yb/n-Si light-emitting diodes. These results are considered an effective strategy for rare-earth-doped semiconductor electroluminescence in near-infrared light-emitting diodes.

掺杂稀土（RE）的氧化锌电致发光因其纯净而锐利的发光特性而值得研究。在这项工作中，我们报告了氧化锌：镱发光二极管（LED），并测试了它们的电致发光特性。通过调整掺杂镱的浓度和优化 ZnO:Yb 薄膜的退火参数，结果表明 ZnO:Yb 发光二极管能够在 975 nm 和 1004 nm 处产生强烈的近红外发射。我们认为，冲击激发是 ITO/PEDOT:PSS/ZnO:Yb/n-Si 发光二极管电致发光的主要机制。这些结果被认为是在近红外发光二极管中实现稀土掺杂半导体电致发光的有效策略。

引用次数: 0

Traps characterization in RF SOI substrates including a buried SiGe layer 射频 SOI 基底（包括埋入的 SiGe 层）中的陷波表征

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-03-11 DOI: 10.1016/j.sse.2025.109103

Y. Yan , M. Rack , M. Vanbrabant , M. Nabet , A. Goebel , P. Clifton , J.-P. Raskin

This work analyzes the interface traps density (D_it) at the SiO₂/SiGe interface of a buried SiGe stressor SOI substrate, and demonstrates the impact of those traps on the effective resistivity (ρ_eff) of the substrate. The C-V behavior of MOS capacitors and the RF insertion loss along coplanar waveguide transmission lines on various substrates are measured. TCAD simulations are employed to interpret the traps characteristics and to forecast the RF performance of a buried SiGe stressor SOI wafer having a high resistivity handle Si substrate. The results demonstrate that thanks to the interface traps introduced by the SiGe layer the substrate effective resistivity (ρ_eff) is enhanced.

引用次数: 0

Low power consumption of non-volatile memory device by tunneling process engineering

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-03-09 DOI: 10.1016/j.sse.2025.109100

Fucheng Wang , Mengmeng Chu , Jingwen Chen , Zhong Pan , Yongsang Kim , Jang kun Song , Muhammad Quddamah Khokhar , Junsin Yi

Compared with Si₃N₄ and Al₂O₃, SiO₂ grown using thermal oxidation process as tunneling layer has the advantages of high bandgap and well interface contact with the surface of silicon wafer, which can be a great solution to the leakage current problem of metal–insulator-semiconductor (MIS) devices. This study investigates the effect of improving the SiO₂ tunnel layer on the operating voltage of MIS devices with a SiO₂/HfAlO_x/Al₂O₃ structure. The result shows the operating voltage changes as the tunneling layer thickness decreases, with a minimum of only 12 V for a 1.5 nm tunneling layer thickness. In addition, we found that pinholes are generated on the film surface when annealing a 1.5 nm SiO₂ tunnel layer at 850 °C N₂, in which case the operating voltage of the device is reduced to only 10 V, though it was also accompanied by the deterioration of the retention characteristics.

{"title":"Low power consumption of non-volatile memory device by tunneling process engineering","authors":"Fucheng Wang , Mengmeng Chu , Jingwen Chen , Zhong Pan , Yongsang Kim , Jang kun Song , Muhammad Quddamah Khokhar , Junsin Yi","doi":"10.1016/j.sse.2025.109100","DOIUrl":"10.1016/j.sse.2025.109100","url":null,"abstract":"<div><div>Compared with Si<sub>3</sub>N<sub>4</sub> and Al<sub>2</sub>O<sub>3</sub>, SiO<sub>2</sub> grown using thermal oxidation process as tunneling layer has the advantages of high bandgap and well interface contact with the surface of silicon wafer, which can be a great solution to the leakage current problem of metal–insulator-semiconductor (MIS) devices. This study investigates the effect of improving the SiO<sub>2</sub> tunnel layer on the operating voltage of MIS devices with a SiO<sub>2</sub>/HfAlO<sub>x</sub>/Al<sub>2</sub>O<sub>3</sub> structure. The result shows the operating voltage changes as the tunneling layer thickness decreases, with a minimum of only 12 V for a 1.5 nm tunneling layer thickness. In addition, we found that pinholes are generated on the film surface when annealing a 1.5 nm SiO<sub>2</sub> tunnel layer at 850 °C N<sub>2</sub>, in which case the operating voltage of the device is reduced to only 10 V, though it was also accompanied by the deterioration of the retention characteristics.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109100"},"PeriodicalIF":1.4,"publicationDate":"2025-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143627960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Selective grain size enlargement in Contact/Via plugs using Nanosecond green laser annealing 利用纳秒绿色激光退火技术有选择地增大接触/Via 塞的晶粒尺寸

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-03-07 DOI: 10.1016/j.sse.2025.109098

Jaejoong Jeong , Youngkeun Park , Hwanuk Guim , Yongku Baek , Heetae Kim , Dongbin Kim , Hui Jae Cho , Su-hyeon Gwon , Min Ju Kim , Byung Jin Cho

The rapid decrease in interconnect Critical Dimensions (CDs) within logic devices and growth in the contact height of 3D memory devices have led to increased contact/via plugs resistance. In this study, we introduce an approach to reduce the resistance of the contact/via plugs by engineering the grain size of the plugs using Nanosecond Green Laser Annealing (NGLA) with a low energy fluence (= 0.1 J/cm²). Because of the proximity between adjacent W plugs, diffraction of the laser light can occur which will help the laser energy to be absorbed by the sidewall of the W plugs. In addition, the difference in reflectivity between the plug region and W interconnect lines can cause grain size enlargement to selectively occur in the plug region. The NGLA process increased grain size in the plugs up to 79.9 %, resulting as much as a 26 % reduction in tungsten plug resistance. The standard deviation of the plug resistance was also improved from 14.6 % to 7.9 % after the NGLA process.

{"title":"Selective grain size enlargement in Contact/Via plugs using Nanosecond green laser annealing","authors":"Jaejoong Jeong , Youngkeun Park , Hwanuk Guim , Yongku Baek , Heetae Kim , Dongbin Kim , Hui Jae Cho , Su-hyeon Gwon , Min Ju Kim , Byung Jin Cho","doi":"10.1016/j.sse.2025.109098","DOIUrl":"10.1016/j.sse.2025.109098","url":null,"abstract":"<div><div>The rapid decrease in interconnect Critical Dimensions (CDs) within logic devices and growth in the contact height of 3D memory devices have led to increased contact/via plugs resistance. In this study, we introduce an approach to reduce the resistance of the contact/via plugs by engineering the grain size of the plugs using Nanosecond Green Laser Annealing (NGLA) with a low energy fluence (= 0.1 J/cm<sup>2</sup>). Because of the proximity between adjacent W plugs, diffraction of the laser light can occur which will help the laser energy to be absorbed by the sidewall of the W plugs. In addition, the difference in reflectivity between the plug region and W interconnect lines can cause grain size enlargement to selectively occur in the plug region. The NGLA process increased grain size in the plugs up to 79.9 %, resulting as much as a 26 % reduction in tungsten plug resistance. The standard deviation of the plug resistance was also improved from 14.6 % to 7.9 % after the NGLA process.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109098"},"PeriodicalIF":1.4,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143620325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-frequency noise in polysilicon Source-Gated Thin-Film transistors

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-03-03 DOI: 10.1016/j.sse.2025.109099

Q. Chen , L.Van Brandt , V. Kilchytska , E. Bestelink , R.A. Sporea , D. Flandre

The low-frequency noise (LFN) of thin-film polysilicon source-gated transistors (SGTs) is investigated. DC characteristics were firstly measured and typical behaviors of SGT were observed. Then, TCAD simulations were performed with different doping concentrations. Current density distribution shows that the variation of the conduction channel position in the thin film induces a second plateau in the (g_m/I_D)² curves for bias points in subthreshold region. LFN was measured for both SGTs and thin-film field-effect transistor (TFTs) configurations. 1/f noise is confirmed as the main component of LFN in all our measurements. Carrier mobility fluctuation (CMF) is found to dominate the origin of LFN in TFT configuration and the low-current region of SGT. In the high-current region of SGT measurements, 1/f noise is mainly attributed to carrier number fluctuation (CNF).

引用次数: 0

High-endurance bulk CMOS one-transistor cryo-memory

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-02-28 DOI: 10.1016/j.sse.2025.109097

A. Zaslavsky , P.R. Shrestha , V.Ortiz Jimenez , J.P. Campbell , C.A. Richter

Previously we reported a compact one-transistor (1 T) 180 nm bulk CMOS cryo-memory with a high ≈10⁷ I₁/I₀ memory window and long ≈800 s retention time based on impact-ionization-induced charging of the transistor body. Here, we present the endurance and retention characteristics of our 1 T memory obtained from high-speed measurements at T = 7 K. We observe excellent endurance, with no visible degradation over 10⁹ write ‘1′/write ‘0′ cycles. The measured retention time varies with the memory window and the leakage current, but it exceeds 10 s for a 30X I₁/I₀ memory window and would be even higher in a device with no substrate contact.

引用次数: 0

Investigation of reconfigurable logic gate using integrated amorphous InGaZnO ReRAM and thin-film transistor

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-02-19 DOI: 10.1016/j.sse.2025.109084

Jung Rae Cho , Jingyu Park , Seung Joo Myoung , Tae Jun Yang , Changwook Kim , Jong-Ho Bae , Sung-Jin Choi , Dong Myong Kim , Ickhyun Song , Dae Hwan Kim

This paper proposes a new reconfigurable logic circuits based on InGaZnO resistive random-access memory (ReRAM) and presents a comprehensive investigation of their electrical characteristics and logic operation. Two fundamental equations that govern the transport mechanism of oxygen ions were utilized to model the formation of lateral and vertical conducting filaments in ReRAM devices in a circuit simulation environment. Based on the device models, the electrical behavior of ReRAM was examined and verified, using circuit simulators. Experimental results from dc current–voltage and pulse measurements of ReRAM and thin-film transistors (TFTs) demonstrate their electrical switching characteristics. The paper analyzes and validates the operation of two ReRAM-based logic configurations: 1 T-1 M (one transistor and one ReRAM cell) and 2 T-2 M−INV (inverter). A detailed analysis were conducted to compare the proposed ReRAM-based logic with the conventional CMOS counterparts, revealing favorable advantages in reducing transistor counts and die areas. The 1 T-1 M and 2 T-2 M−INV exhibit reconfigurable logic operations under different resistive states of ReRAM cells. Additionally, the investigations of short-circuit current profiles shows the superior performance of ReRAM-based logic gates to the CMOS counterpart in terms of power consumption. Overall, this study investigates the feasibility of ReRAM-based reconfigurable logic circuits for future low-power and high-performance computing applications.

{"title":"Investigation of reconfigurable logic gate using integrated amorphous InGaZnO ReRAM and thin-film transistor","authors":"Jung Rae Cho , Jingyu Park , Seung Joo Myoung , Tae Jun Yang , Changwook Kim , Jong-Ho Bae , Sung-Jin Choi , Dong Myong Kim , Ickhyun Song , Dae Hwan Kim","doi":"10.1016/j.sse.2025.109084","DOIUrl":"10.1016/j.sse.2025.109084","url":null,"abstract":"<div><div>This paper proposes a new reconfigurable logic circuits based on InGaZnO resistive random-access memory (ReRAM) and presents a comprehensive investigation of their electrical characteristics and logic operation. Two fundamental equations that govern the transport mechanism of oxygen ions were utilized to model the formation of lateral and vertical conducting filaments in ReRAM devices in a circuit simulation environment. Based on the device models, the electrical behavior of ReRAM was examined and verified, using circuit simulators. Experimental results from dc current–voltage and pulse measurements of ReRAM and thin-film transistors (TFTs) demonstrate their electrical switching characteristics. The paper analyzes and validates the operation of two ReRAM-based logic configurations: 1 T-1 M (one transistor and one ReRAM cell) and 2 T-2 M−INV (inverter). A detailed analysis were conducted to compare the proposed ReRAM-based logic with the conventional CMOS counterparts, revealing favorable advantages in reducing transistor counts and die areas. The 1 T-1 M and 2 T-2 M−INV exhibit reconfigurable logic operations under different resistive states of ReRAM cells. Additionally, the investigations of short-circuit current profiles shows the superior performance of ReRAM-based logic gates to the CMOS counterpart in terms of power consumption. Overall, this study investigates the feasibility of ReRAM-based reconfigurable logic circuits for future low-power and high-performance computing applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109084"},"PeriodicalIF":1.4,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143487699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparison of radiation effects of LM and UMM structure GaAs triple-junction solar cells under 1 MeV neutron irradiation

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-02-14 DOI: 10.1016/j.sse.2025.109087

Minqiang Liu , Xuqiang Liu , Guoping Xiao , Bobo Wang , Sanyong Zou , Le Zhong , Xianguo Xu , Chao Zeng , Shuyi Zhang , Guanghai Tang , Fang Deng , Abuduwayiti Aierken

The output performances of lattice-matched (LM) and upright metamorphic (UMM) GaAs triple-junction solar cells under 1 MeV neutron irradiation were studied. The results show that the electrical performance, including open-circuit voltage, short-circuit current, maximum output power and fill factor of the solar cells were degraded seriously with the increase of neutron irradiation fluence. Meanwhile, the series resistance and the shunt resistance of solar cells are increased and decreased, respectively, when the neutron irradiation fluence increased. The degradation of maximum output power in LM and UMM GaAs cells is about the same level of 72.9 % and 72.3 % of its initial values, respectively, when the irradiation fluence is reached 6 × 10¹² n/cm². By comparing the integrated current densities, it was found out that the current-limiting subcell in LM cells s always GaAs middle cell, and in the UMM cell, the current limiting unit is changed from GaInP top subcell to GaInAs middle subcell after high fluence neutron irradiation.

研究了晶格匹配（LM）和直立变质（UMM）砷化镓三结太阳能电池在 1 MeV 中子辐照下的输出性能。结果表明，随着中子辐照通量的增加，太阳能电池的电气性能（包括开路电压、短路电流、最大输出功率和填充因子）严重下降。同时，随着中子辐照通量的增加，太阳能电池的串联电阻和并联电阻分别增大和减小。当辐照通量达到 6 × 1012 n/cm2 时，LM 和 UMM GaAs 电池的最大输出功率衰减基本相同，分别为初始值的 72.9% 和 72.3%。通过比较综合电流密度，可以发现 LM 电池中的限流子单元始终是 GaAs 中间单元，而在 UMM 电池中，经过高通量中子辐照后，限流单元从 GaInP 顶部子单元变为 GaInAs 中间子单元。

{"title":"Comparison of radiation effects of LM and UMM structure GaAs triple-junction solar cells under 1 MeV neutron irradiation","authors":"Minqiang Liu , Xuqiang Liu , Guoping Xiao , Bobo Wang , Sanyong Zou , Le Zhong , Xianguo Xu , Chao Zeng , Shuyi Zhang , Guanghai Tang , Fang Deng , Abuduwayiti Aierken","doi":"10.1016/j.sse.2025.109087","DOIUrl":"10.1016/j.sse.2025.109087","url":null,"abstract":"<div><div>The output performances of lattice-matched (LM) and upright metamorphic (UMM) GaAs triple-junction solar cells under 1 MeV neutron irradiation were studied. The results show that the electrical performance, including open-circuit voltage, short-circuit current, maximum output power and fill factor of the solar cells were degraded seriously with the increase of neutron irradiation fluence. Meanwhile, the series resistance and the shunt resistance of solar cells are increased and decreased, respectively, when the neutron irradiation fluence increased. The degradation of maximum output power in LM and UMM GaAs cells is about the same level of 72.9 % and 72.3 % of its initial values, respectively, when the irradiation fluence is reached 6 × 10<sup>12</sup> n/cm<sup>2</sup>. By comparing the integrated current densities, it was found out that the current-limiting subcell in LM cells s always GaAs middle cell, and in the UMM cell, the current limiting unit is changed from GaInP top subcell to GaInAs middle subcell after high fluence neutron irradiation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109087"},"PeriodicalIF":1.4,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143437754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Influence of temperature inhomogeneity and trap charge on current imbalance of SiC MOSFETs

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-02-12 DOI: 10.1016/j.sse.2025.109085

Chunsheng Guo, Jiapeng Li, Yamin Zhang, Hui Zhu, Meng Zhang, Shiwei Feng

For SiC MOSFETs, either multi-chip modules or multiple discrete devices need to be connected in parallel to achieve high current capacities. However, the current imbalance that occurs in parallel applications can reduce device reliability. This paper focused on the effects of both temperature inhomogeneity and gate trap charge on the current imbalance behavior of SiC MOSFETs, and it also presented a comparison study of the effects of threshold voltage differences on the current inhomogeneity. Finally, the effects of the three factors above on the current inhomogeneity characteristics of SiC MOSFETs were compared in terms of their voltage and time dimensions. The results show that the percentage of the drain-source current imbalance due to temperature inhomogeneity for static processes can be maintained consistently at more than 10%. For dynamic processes, the percentage of the drain-source current imbalance due to temperature inhomogeneity can similarly exceed 10%.

引用次数: 0

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