Pub Date : 2026-01-27DOI: 10.1016/j.sse.2026.109342
Evan T. Salim , Rana O. Mahdi , Roaa A. Abbas , Zaid T. Salim , Subash C.B. Gopinath , Ahmed A. Al-Amiery
Hydrothermally formed silver-decorated cuprous oxide thin films were synthesized at different Ag concentrations. The optimum condition sample was used for the formation of high-performance optoelectronic devices, which show enhancements in the pure Cu2O/p-Si heterojunction device. Structural properties studied by XRD show successful decoration on the Cu2O surface, with Ag decoration inducing a controlled reduction in Cu2O crystallite size (33.4 to 30.4 nm). Notably, silver decoration produced a strategy for band gap narrowing from 2.29 to 2.12 eV, while SERS analysis shows signal enhancement for Ag decorated cuprous oxide in comparison with pure Cu2O.
The optimum condition was obtained from a sample of 0.01 g, which was used for the synthesis of Ag@Cu2O/p-Si heterojunction to enhance the photodetector properties, including a responsivity, detectivity, and quantum efficiency. The built-in potential of 1.4 V compared with pure Cu2O/p-Si. This configuration of the device produces an enhancement in the responsivity across the visible to near-IR spectrum.
{"title":"Ag-Cu2O nano composite: A comprehensive study on Ag concentration effect on physical properties for a two-band laser detector","authors":"Evan T. Salim , Rana O. Mahdi , Roaa A. Abbas , Zaid T. Salim , Subash C.B. Gopinath , Ahmed A. Al-Amiery","doi":"10.1016/j.sse.2026.109342","DOIUrl":"10.1016/j.sse.2026.109342","url":null,"abstract":"<div><div>Hydrothermally formed silver-decorated cuprous oxide thin films were synthesized at different Ag concentrations. The optimum condition sample was used for the formation of high-performance optoelectronic devices, which show enhancements in the pure Cu<sub>2</sub>O/p-Si heterojunction device. Structural properties studied by XRD show successful decoration on the Cu2O surface, with Ag decoration inducing a controlled reduction in Cu<sub>2</sub>O crystallite size (33.4 to 30.4 nm). Notably, silver decoration produced a strategy for band gap narrowing from 2.29 to 2.12 eV, while SERS analysis shows signal enhancement for Ag decorated cuprous oxide in comparison with pure Cu2O.</div><div>The optimum condition was obtained from a sample of 0.01 g, which was used for the synthesis of Ag@Cu<sub>2</sub>O/p-Si heterojunction to enhance the photodetector properties, including a responsivity, detectivity, and quantum efficiency. The built-in potential of 1.4 V compared with pure Cu<sub>2</sub>O/p-Si. This configuration of the device produces an enhancement in the responsivity across the visible to near-IR spectrum.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"234 ","pages":"Article 109342"},"PeriodicalIF":1.4,"publicationDate":"2026-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146081895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-20DOI: 10.1016/j.sse.2026.109334
Haruki Yoshida, Takashi Onaya, Atsushi Tamura, Koji Kita
Thermal nitridation is the most common method for SiC surface defect passivation by introducing nitrogen on the surface, however, the nitridation process using active species such as N-radicals is one of the possible alternatives. This study investigated the kinetics of nitridation on SiC surface by N-radicals and compared them with those of thermal nitridation. Both processes showed a saturation of surface N density after prolonged nitridation, which is explainable by considering the competition between N-incorporation and N-desorption. N-desorption is driven by surface oxidation in the case of thermal nitridation, whereas it is caused by a heating in a high vacuum environment in the case of N-radical nitridation. In addition, N-incorporation rate reduction due to the depletion of surface reactive sites as surface N density increases must be taken into account in the case of radical nitridation.
{"title":"Difference in kinetics between thermal nitridation and radical nitridation processes of 4H-SiC surface considering simultaneous N-incorporation and N-desorption reactions","authors":"Haruki Yoshida, Takashi Onaya, Atsushi Tamura, Koji Kita","doi":"10.1016/j.sse.2026.109334","DOIUrl":"10.1016/j.sse.2026.109334","url":null,"abstract":"<div><div>Thermal nitridation is the most common method for SiC surface defect passivation by introducing nitrogen on the surface, however, the nitridation process using active species such as N-radicals is one of the possible alternatives. This study investigated the kinetics of nitridation on SiC surface by N-radicals and compared them with those of thermal nitridation. Both processes showed a saturation of surface N density after prolonged nitridation, which is explainable by considering the competition between N-incorporation and N-desorption. N-desorption is driven by surface oxidation in the case of thermal nitridation, whereas it is caused by a heating in a high vacuum environment in the case of N-radical nitridation. In addition, N-incorporation rate reduction due to the depletion of surface reactive sites as surface N density increases must be taken into account in the case of radical nitridation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109334"},"PeriodicalIF":1.4,"publicationDate":"2026-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146023139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, low-k/high-k multilayers were developed to improve the electrical performance of capacitors in high-voltage applications. SiOCH/HfO2 stacks were deposited by PECVD and ALD at 300°C on 200 mm Si wafers achieving a total thickness of around 115 nm, with variations in the number of layers and the capacitor area. The results show that the dielectric layers are continuous and of good quality. Using the multilayer approach of alternating SiOCH and HfO2 layers, the dielectric constant and breakdown strength are significantly improved compared to a single SiOCH layer, without degrading the dielectric losses. This strategy seems promising for high-voltage capacitors.
在这项工作中，开发了低k/高k多层材料，以改善高压应用中电容器的电性能。SiOCH/HfO2堆栈通过PECVD和ALD在300°C下沉积在200 mm Si晶圆上，总厚度约为115 nm，层数和电容器面积有所变化。结果表明，介质层连续且质量良好。使用SiOCH和HfO2交替的多层方法，与单一SiOCH层相比，介电常数和击穿强度显着提高，而介电损耗不降低。这种策略对于高压电容器似乎很有希望。
{"title":"Exploring low-k/high-k multilayers as high breakdown strength dielectrics for capacitors","authors":"Julie Chaussard , Chloé Guérin , Aude Lefèvre , Patrice Gonon , Vincent Jousseaume","doi":"10.1016/j.sse.2026.109331","DOIUrl":"10.1016/j.sse.2026.109331","url":null,"abstract":"<div><div>In this work, low-k/high-k multilayers were developed to improve the electrical performance of capacitors in high-voltage applications. SiOCH/HfO<sub>2</sub> stacks were deposited by PECVD and ALD at 300°C on 200 mm Si wafers achieving a total thickness of around 115 nm, with variations in the number of layers and the capacitor area. The results show that the dielectric layers are continuous and of good quality. Using the multilayer approach of alternating SiOCH and HfO<sub>2</sub> layers, the dielectric constant and breakdown strength are significantly improved compared to a single SiOCH layer, without degrading the dielectric losses. This strategy seems promising for high-voltage capacitors.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109331"},"PeriodicalIF":1.4,"publicationDate":"2026-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146023138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-13DOI: 10.1016/j.sse.2026.109333
Shuangjia Bai , Taifu Lang , Xin Lin , Shuaishuai Wang , Zhihua Wang , Chang Lin , Qun Yan , Jie Sun
This study proposes an innovative wet reflow process utilizing SU-8 photoresist as the solder mask for fabricating In bump arrays in Micro LED packaging. Conventional solder masks such as SiO2 or metal layers involve complex processes, elevated temperatures, and limited compatibility with flexible substrates. In contrast, SU-8 enables mask patterning via single-step UV lithography, greatly simplifying fabrication and effectively reducing manufacturing complexity and cost. The optimized process achieved a 480 × 640 In bump array with excellent morphology: surface roughness (Ra) reduced from 0.65 μm to 0.126 μm, height non-uniformity improved from 4.8 % to 0.28 %, and shear strength increased nearly tenfold to 1.106 N. Using glycerol as an eco-friendly wet reflow medium facilitated oxide mitigation and enhanced bump uniformity and bonding reliability. The results demonstrate that this low-temperature, efficient, and scalable approach offers clear advantages for high-yield Micro LED integration, particularly in flexible and high-resolution display applications.
{"title":"Bonding of micro LEDs using wet reflow process of indium bumps based on SU-8 solder mask","authors":"Shuangjia Bai , Taifu Lang , Xin Lin , Shuaishuai Wang , Zhihua Wang , Chang Lin , Qun Yan , Jie Sun","doi":"10.1016/j.sse.2026.109333","DOIUrl":"10.1016/j.sse.2026.109333","url":null,"abstract":"<div><div>This study proposes an innovative wet reflow process utilizing SU-8 photoresist as the solder mask for fabricating In bump arrays in Micro LED packaging. Conventional solder masks such as SiO<sub>2</sub> or metal layers involve complex processes, elevated temperatures, and limited compatibility with flexible substrates. In contrast, SU-8 enables mask patterning via single-step UV lithography, greatly simplifying fabrication and effectively reducing manufacturing complexity and cost. The optimized process achieved a 480 × 640 In bump array with excellent morphology: surface roughness (R<sub>a</sub>) reduced from 0.65 μm to 0.126 μm, height non-uniformity improved from 4.8 % to 0.28 %, and shear strength increased nearly tenfold to 1.106 N. Using glycerol as an eco-friendly wet reflow medium facilitated oxide mitigation and enhanced bump uniformity and bonding reliability. The results demonstrate that this low-temperature, efficient, and scalable approach offers clear advantages for high-yield Micro LED integration, particularly in flexible and high-resolution display applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"234 ","pages":"Article 109333"},"PeriodicalIF":1.4,"publicationDate":"2026-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146049119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-11DOI: 10.1016/j.sse.2026.109332
Dominik Kleimaier , Stefan Dünkel , Halid Mulaosmanovic , Johannes Müller , Sven Beyer , Viktor Havel , Thomas Mikolajick
This study investigates the short-term (µs to s timespan) charge trapping effects in hafnium oxide-based ferroelectric field-effect transistors, integrated within GlobalFoundries’ 28 nm bulk high-k metal gate (HKMG) technology.
Even without ferroelectric switching, positive gate voltage pulses can cause significant short-term electron trapping due to strong energy band bending that enables charge injection.
A systematic analysis reveals that the extent of short-term trapping increases with both the amplitude and the duration of the applied gate pulses. These dependencies are consolidated into a positive bias charge trapping matrix, offering an overview of how various factors collectively influence trapping behavior. Negative gate bias does not cause charge trapping in FeFETs for the investigated voltage and time domain.
Building on previous reports of degradation-free unipolar endurance cycling, these observations further support the conclusion that the pronounced short-term trapping effects are primarily non-destructive.
The study highlights the importance of understanding and accounting for short-term charge trapping effects, especially as they relate to read-after-write capabilities and overlaps with switching mechanisms. This understanding is crucial for optimizing the consistent and effective operation of FeFETs as memory cells and neuromorphic computing elements.
{"title":"Short-term charge trapping effects in ferroelectric FETs: impact of pulse amplitude and timing","authors":"Dominik Kleimaier , Stefan Dünkel , Halid Mulaosmanovic , Johannes Müller , Sven Beyer , Viktor Havel , Thomas Mikolajick","doi":"10.1016/j.sse.2026.109332","DOIUrl":"10.1016/j.sse.2026.109332","url":null,"abstract":"<div><div>This study investigates the short-term (µs to s timespan) charge trapping effects in hafnium oxide-based ferroelectric field-effect transistors, integrated within GlobalFoundries’ 28 <!--> <!-->nm bulk high-k metal gate (HKMG) technology.</div><div>Even without ferroelectric switching, positive gate voltage pulses can cause significant short-term electron trapping due to strong energy band bending that enables charge injection.</div><div>A systematic analysis reveals that the extent of short-term trapping increases with both the amplitude and the duration of the applied gate pulses. These dependencies are consolidated into a positive bias charge trapping matrix, offering an overview of how various factors collectively influence trapping behavior. Negative gate bias does not cause charge trapping in FeFETs for the investigated voltage and time domain.</div><div>Building on previous reports of degradation-free unipolar endurance cycling, these observations further support the conclusion that the pronounced short-term trapping effects are primarily non-destructive.</div><div>The study highlights the importance of understanding and accounting for short-term charge trapping effects, especially as they relate to read-after-write capabilities and overlaps with switching mechanisms. This understanding is crucial for optimizing the consistent and effective operation of FeFETs as memory cells and neuromorphic computing elements.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109332"},"PeriodicalIF":1.4,"publicationDate":"2026-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01DOI: 10.1016/j.sse.2025.109329
Karimul Islam , Rezwana Sultana , Aleksandra Dzięgielewska , Robert Mroczyński
This study investigates the influence of the top metal electrode on the resistive switching (RS) behavior of the metal/TiOx/ITO structure. Specifically, the effects of Al and TiN as top electrodes were examined in devices utilizing a 30 nm TiOx thin film as the active layer, deposited using a pulsed-DC reactive sputtering technique. Both configurations exhibited non-volatile bipolar resistive switching, demonstrating endurance over 100 cycles and stable data retention (>104 s). The results indicate that the choice of top electrode (TE) plays a crucial role in determining the electroforming process, current conduction mechanisms, and overall RS performance. Notably, devices with TiN as a TE exhibited more consistent RS behavior, with a superior ON/OFF ratio and enhanced operational stability. These findings demonstrate that electrode engineering offers a viable pathway to enhance resistive switching performance. The insights gained from this study provide a basis for the rational design and optimization of CMOS-compatible TiOx-based resistive random-access memory (RRAM) devices.
{"title":"Impact of top electrode materials on resistive switching characteristics of TiOx-based MIM structures","authors":"Karimul Islam , Rezwana Sultana , Aleksandra Dzięgielewska , Robert Mroczyński","doi":"10.1016/j.sse.2025.109329","DOIUrl":"10.1016/j.sse.2025.109329","url":null,"abstract":"<div><div>This study investigates the influence of the top metal electrode on the resistive switching (RS) behavior of the metal/TiO<sub>x</sub>/ITO structure. Specifically, the effects of Al and TiN as top electrodes were examined in devices utilizing a 30 nm TiO<sub>x</sub> thin film as the active layer, deposited using a pulsed-DC reactive sputtering technique. Both configurations exhibited non-volatile bipolar resistive switching, demonstrating endurance over 100 cycles and stable data retention (>10<sup>4</sup> s). The results indicate that the choice of top electrode (TE) plays a crucial role in determining the electroforming process, current conduction mechanisms, and overall RS performance. Notably, devices with TiN as a TE exhibited more consistent RS behavior, with a superior ON/OFF ratio and enhanced operational stability. These findings demonstrate that electrode engineering offers a viable pathway to enhance resistive switching performance. The insights gained from this study provide a basis for the rational design and optimization of CMOS-compatible TiO<sub>x</sub>-based resistive random-access memory (RRAM) devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109329"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145927752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01DOI: 10.1016/j.sse.2025.109330
Joao Antonio Martino , Julius Andretti Peixoto Pires de Paula , Paula Ghedini Der Agopian , Romain Ritzenthaler , Hans Mertens , Anabela Veloso , Naoto Horiguchi
This work presents, for the first time, experimental data on forksheet transistor used in the design of operational transconductance amplifiers (OTA), highlighting their potential for application in analog circuits. The OTA was designed for three different transistor efficiencies: gm/ID of 5, 8 and 11 V−1. The experimental n-type forksheet used in this work presents a sheet thickness of HFS = 7 nm, sheet width of WFS = 23 nm and a transistor channel length of LG = 70 nm. When the gm/ID increases from 5 to 11 V−1, the drain current and the transconductance decrease, which improves the OTA voltage gain (Av ∝ gm/ID) from 49 dB to 63 dB, the total power dissipation (Power ∝ ID) also improves (decreases) from 528 μW to 129 μW, while degrades the Gain-Bandwidth Product (GBW) from 343 MHz to 196 MHz (GBW ∝ gm). Depending on the application, the OTA bias conditions must be set appropriately due to the trade-off between Av and GBW. The obtained results show that the forksheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits using this technology.
{"title":"Application of forksheet transistor in operational transconductance amplifier","authors":"Joao Antonio Martino , Julius Andretti Peixoto Pires de Paula , Paula Ghedini Der Agopian , Romain Ritzenthaler , Hans Mertens , Anabela Veloso , Naoto Horiguchi","doi":"10.1016/j.sse.2025.109330","DOIUrl":"10.1016/j.sse.2025.109330","url":null,"abstract":"<div><div>This work presents, for the first time, experimental data on forksheet transistor used in the design of operational transconductance amplifiers (OTA), highlighting their potential for application in analog circuits. The OTA was designed for three different transistor efficiencies: gm/I<sub>D</sub> of 5, 8 and 11 V<sup>−1</sup>. The experimental n-type forksheet used in this work presents a sheet thickness of H<sub>FS</sub> = 7 nm, sheet width of W<sub>FS</sub> = 23 nm and a transistor channel length of L<sub>G</sub> = 70 nm. When the gm/I<sub>D</sub> increases from 5 to 11 V<sup>−1</sup>, the drain current and the transconductance decrease, which improves the OTA voltage gain (Av ∝ gm/I<sub>D</sub>) from 49 dB to 63 dB, the total power dissipation (Power ∝ I<sub>D</sub>) also improves (decreases) from 528 μW to 129 μW, while degrades the Gain-Bandwidth Product (GBW) from 343 MHz to 196 MHz (GBW ∝ gm). Depending on the application, the OTA bias conditions must be set appropriately due to the trade-off between Av and GBW. The obtained results show that the forksheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits using this technology.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109330"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-30DOI: 10.1016/j.sse.2025.109326
Sekhar Reddy Kola , Min-Hui Chuang , Yiming Li
Variability in gate-all-around (GAA) silicon nanosheet (Si NS) complementary field-effect transistors (CFETs) stems from two primary sources: process-variation effect (PVE) and intrinsic parameter fluctuations (IPF). In this work, a systematic TCAD-based variability framework is developed to quantitatively assess the impact of PVE and IPF on the analog and radio frequency (RF) performance of vertically stacked GAA Si NS CFETs. Key geometrical factors—namely NS thickness (TNS), width (WNS), and gate length (LG)—play a pivotal role in shaping intrinsic resistance (ro), output resistance (Rout), voltage gain (AV), cut-off frequency (fT), and 3-dB bandwidth (f3dB), due to their influence on surface potential profiles and carrier transport behavior. Notably, within IPF, variations are predominantly governed by random nanoscale metal grains, where work function fluctuations (WKF) strongly perturb the channel surface potential, thereby inducing significant variability in AV, fT, f3dB, other radio RF parameters. A statistically significant ensemble of calibrated device simulations is employed to decouple and quantify the individual and combined contributions of PVE and IPF. Furthermore, small-signal s-parameter analysis is performed to extract RF figures of merit under realistic loading conditions, providing practical design insights for variability-aware CFET optimizations.
栅极全能（GAA）硅纳米片互补场效应晶体管（cfet）的可变性主要来自两个方面：工艺变化效应（PVE）和内在参数波动（IPF）。在这项工作中，开发了一个系统的基于tcad的可变性框架，以定量评估PVE和IPF对垂直堆叠GAA Si NS cfet模拟和射频（RF）性能的影响。关键的几何因素-即NS厚度（TNS），宽度（WNS）和栅极长度(LG) -由于其对表面电位分布和载流子输运行为的影响，在形成固有电阻（ro），输出电阻（route），电压增益（AV），截止频率（fT）和3db带宽（f3dB）中起关键作用。值得注意的是，在IPF中，变化主要由随机纳米级金属颗粒控制，其中功函数波动（WKF）强烈干扰通道表面电位，从而诱导AV、fT、f3dB和其他射频参数的显著变化。采用统计上显著的校准设备模拟集合来解耦和量化PVE和IPF的单独和联合贡献。此外，还进行了小信号s参数分析，以提取实际负载条件下的RF值，为可变感知的CFET优化提供实用的设计见解。
{"title":"Radio-frequency variability of GAA Si NS CFETs induced by PVE and IPF simultaneously","authors":"Sekhar Reddy Kola , Min-Hui Chuang , Yiming Li","doi":"10.1016/j.sse.2025.109326","DOIUrl":"10.1016/j.sse.2025.109326","url":null,"abstract":"<div><div>Variability in gate-all-around (GAA) silicon nanosheet (Si NS) complementary field-effect transistors (CFETs) stems from two primary sources: process-variation effect (<em>PVE</em>) and intrinsic parameter fluctuations (<em>IPF</em>). In this work, a systematic TCAD-based variability framework is developed to quantitatively assess the impact of PVE and IPF on the analog and radio frequency (RF) performance of vertically stacked GAA Si NS CFETs. Key geometrical factors—namely NS thickness (<em>T<sub>NS</sub></em>), width (<em>W<sub>NS</sub></em>), and gate length (<em>L<sub>G</sub></em>)—play a pivotal role in shaping intrinsic resistance (<em>r<sub>o</sub></em>), output resistance (<em>R<sub>out</sub></em>), voltage gain (<em>A<sub>V</sub></em>), cut-off frequency (<em>f<sub>T</sub></em>), and 3-dB bandwidth (<em>f</em><sub>3</sub><em><sub>dB</sub></em>), due to their influence on surface potential profiles and carrier transport behavior. Notably, within <em>IPF</em>, variations are predominantly governed by random nanoscale metal grains, where work function fluctuations (<em>WKF</em>) strongly perturb the channel surface potential, thereby inducing significant variability in <em>A<sub>V</sub></em>, <em>f<sub>T</sub></em>, <em>f</em><sub>3</sub><em><sub>dB</sub></em>, other radio RF parameters. A statistically significant ensemble of calibrated device simulations is employed to decouple and quantify the individual and combined contributions of <em>PVE</em> and <em>IPF</em>. Furthermore, small-signal s-parameter analysis is performed to extract RF figures of merit under realistic loading conditions, providing practical design insights for variability-aware CFET optimizations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109326"},"PeriodicalIF":1.4,"publicationDate":"2025-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-29DOI: 10.1016/j.sse.2025.109327
Ghusoon M. Ali , Kahtan Adnan Hussain , Shahad T. Armoot
This study investigates the electrical sensitivities of warm white Al/pentacene/p-Si/Pd Schottky photodiodes with respect to current–voltage (I-V), capacitance–voltage (C-V), and conductance-voltage (G-V) characteristics. The pentacene thin film is deposited using the vacuum thermal evaporation technique. The energy level parameters of the Schottky junction are estimated through energy band diagrams. Two models are introduced to analyze the forward I-V characteristics of the pentacene Schottky diode: the thermionic emission theory and the space-charge-limited current model, both of which explain the mechanisms of charge carrier transport. The I-V, C-V, and G-V characteristics were examined under both dark and warm white illumination conditions, across a voltage range of −4 to 4 V at room temperature. Moreover, a study was conducted to assess, extract, and compare the sensitivities of current (SI), capacitance (SC), and conductance (SCO). The maximum SI is 1682 % at 0 V. Therefore, the proposed device demonstrates outstanding performance as a self-powered photodetector. The maximum SC is 38 % at −2.1 V, and SCO is 370 % at −1.6 V. The variations in sensitivity values are attributed to the different detection mechanisms employed. Overall, the results demonstrate the significant potential of the current-mode Schottky pentacene diode for use as a warm white self-powered photodetector.
{"title":"Warm white electrical sensitivities of pentacene-based Schottky photodiode","authors":"Ghusoon M. Ali , Kahtan Adnan Hussain , Shahad T. Armoot","doi":"10.1016/j.sse.2025.109327","DOIUrl":"10.1016/j.sse.2025.109327","url":null,"abstract":"<div><div>This study investigates the electrical sensitivities of warm white Al/pentacene/p-Si/Pd Schottky photodiodes with respect to current–voltage (I-V), capacitance–voltage (C-V), and conductance-voltage (G-V) characteristics. The pentacene thin film is deposited using the vacuum thermal evaporation technique. The energy level parameters of the Schottky junction are estimated through energy band diagrams. Two models are introduced to analyze the forward I-V characteristics of the pentacene Schottky diode: the thermionic emission theory and the space-charge-limited current model, both of which explain the mechanisms of charge carrier transport. The I-V, C-V, and G-V characteristics were examined under both dark and warm white illumination conditions, across a voltage range of −4 to 4 V at room temperature. Moreover, a study was conducted to assess, extract, and compare the sensitivities of current (S<sub>I</sub>), capacitance (S<sub>C</sub>), and conductance (S<sub>CO</sub>). The maximum S<sub>I</sub> is 1682 % at 0 V. Therefore, the proposed device demonstrates outstanding performance as a self-powered photodetector. The maximum S<sub>C</sub> is 38 % at −2.1 V, and S<sub>CO</sub> is 370 % at −1.6 V. The variations in sensitivity values are attributed to the different detection mechanisms employed. Overall, the results demonstrate the significant potential of the current-mode Schottky pentacene diode for use as a warm white self-powered photodetector.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109327"},"PeriodicalIF":1.4,"publicationDate":"2025-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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