Solid-state Electronics最新文献

英文中文

Unveiling the output conductance dynamics in Nanosheet FET: Does cryogenic temperature Make a Difference? 揭示纳米片场效应管的输出电导动态：低温是否有影响？

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-06-01 Epub Date: 2026-02-08 DOI: 10.1016/j.sse.2026.109348

Malvika , Prabhat Singh , Navjeet Bagga , Mohd. Shakir , Ankit Dixit , Naveen Kumar , Vihar Georgiev , S. Dasgupta

Channel length modulation (CLM) and drain-induced barrier lowering (DIBL) are well-known short-channel effects that result in a finite output conductance (g_ds). In a simplified analysis, g_ds is predominantly governed by the drain voltage (V_DS) and can be approximated by the slope of the I_DS–V_DS characteristics in the saturation regime. However, will the conceptual governance of g_ds be the same at the cryogenic temperatures? To answer this question, we thoroughly investigate the Cryogenic Nanosheet FET (NSFET) using well-calibrated TCAD models. The results reveal that incomplete ionization in the cryogenic temperature (CT) regime provides additional expansion of the depletion at the drain side. This significantly increases g_ds (i.e., the slope of the IDS-VDS characteristics) in CT compared to that at room temperature (RT). Therefore, in a Cryogenic FET, CLM becomes the function of temperature. Further, we extracted the CLM parameter (λ), early voltage (V_A), and intrinsic gain (g_max/g_ds) of the Nanosheet FET with varying temperatures and found that the g_max/g_ds is maximum at 4 K.

通道长度调制（CLM）和漏极诱导势垒降低（DIBL）是众所周知的导致有限输出电导（gds）的短通道效应。在简化分析中，gds主要由漏极电压（VDS）控制，并且可以通过饱和状态下IDS-VDS特性的斜率来近似。然而，在低温下，神的概念治理是否相同？为了回答这个问题，我们使用校准良好的TCAD模型深入研究了低温纳米片场效应管（NSFET）。结果表明，在低温（CT）状态下，不完全电离提供了漏侧损耗的额外扩展。与室温（RT）相比，这显著增加了CT中的gds（即IDS-VDS特征的斜率）。因此，在低温场效应管中，CLM成为温度的函数。此外，我们提取了不同温度下纳米片场效应管的CLM参数（λ）、早期电压（VA）和本征增益（gmax/gds），发现gmax/gds在4 K时最大。

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引用次数: 0

Bonding of micro LEDs using wet reflow process of indium bumps based on SU-8 solder mask 基于SU-8阻焊膜的铟凸点湿回流焊微型led

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-06-01 Epub Date: 2026-01-13 DOI: 10.1016/j.sse.2026.109333

Shuangjia Bai , Taifu Lang , Xin Lin , Shuaishuai Wang , Zhihua Wang , Chang Lin , Qun Yan , Jie Sun

This study proposes an innovative wet reflow process utilizing SU-8 photoresist as the solder mask for fabricating In bump arrays in Micro LED packaging. Conventional solder masks such as SiO₂ or metal layers involve complex processes, elevated temperatures, and limited compatibility with flexible substrates. In contrast, SU-8 enables mask patterning via single-step UV lithography, greatly simplifying fabrication and effectively reducing manufacturing complexity and cost. The optimized process achieved a 480 × 640 In bump array with excellent morphology: surface roughness (R_a) reduced from 0.65 μm to 0.126 μm, height non-uniformity improved from 4.8 % to 0.28 %, and shear strength increased nearly tenfold to 1.106 N. Using glycerol as an eco-friendly wet reflow medium facilitated oxide mitigation and enhanced bump uniformity and bonding reliability. The results demonstrate that this low-temperature, efficient, and scalable approach offers clear advantages for high-yield Micro LED integration, particularly in flexible and high-resolution display applications.

本研究提出了一种创新的湿回流工艺，利用SU-8光刻胶作为阻焊膜，用于制造微型LED封装中的凹凸阵列。传统的阻焊膜，如SiO2或金属层，涉及复杂的工艺、高温和与柔性基板的有限兼容性。相比之下，SU-8通过单步UV光刻实现掩模图案，大大简化了制造过程，并有效降低了制造复杂性和成本。优化后的凹凸阵列尺寸为480 × 640 In，表面粗糙度（Ra）从0.65 μm降低到0.126 μm，高度不均匀性从4.8 %提高到0.28 %，抗剪强度提高近10倍，达到1.106 N。使用甘油作为环保型湿回流介质有助于减少氧化物，增强凹凸均匀性和粘合可靠性。结果表明，这种低温、高效和可扩展的方法为高产量微型LED集成提供了明显的优势，特别是在灵活和高分辨率显示应用中。

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引用次数: 0

Ag-Cu2O nano composite: A comprehensive study on Ag concentration effect on physical properties for a two-band laser detector Ag- cu2o纳米复合材料：Ag浓度对双波段激光探测器物理性能影响的综合研究

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-06-01 Epub Date: 2026-01-27 DOI: 10.1016/j.sse.2026.109342

Evan T. Salim , Rana O. Mahdi , Roaa A. Abbas , Zaid T. Salim , Subash C.B. Gopinath , Ahmed A. Al-Amiery

Hydrothermally formed silver-decorated cuprous oxide thin films were synthesized at different Ag concentrations. The optimum condition sample was used for the formation of high-performance optoelectronic devices, which show enhancements in the pure Cu₂O/p-Si heterojunction device. Structural properties studied by XRD show successful decoration on the Cu2O surface, with Ag decoration inducing a controlled reduction in Cu₂O crystallite size (33.4 to 30.4 nm). Notably, silver decoration produced a strategy for band gap narrowing from 2.29 to 2.12 eV, while SERS analysis shows signal enhancement for Ag decorated cuprous oxide in comparison with pure Cu2O.

The optimum condition was obtained from a sample of 0.01 g, which was used for the synthesis of Ag@Cu₂O/p-Si heterojunction to enhance the photodetector properties, including a responsivity, detectivity, and quantum efficiency. The built-in potential of 1.4 V compared with pure Cu₂O/p-Si. This configuration of the device produces an enhancement in the responsivity across the visible to near-IR spectrum.

在不同的银浓度下，水热法制备了镀银氧化亚铜薄膜。采用最佳条件制备的样品制备了高性能光电子器件，在纯Cu2O/p-Si异质结器件中表现出增强效应。XRD分析表明，在Cu2O表面进行了成功的修饰，Ag修饰使Cu2O晶粒尺寸可控地减小（33.4 ~ 30.4 nm）。值得注意的是，银修饰使带隙从2.29 eV缩小到2.12 eV，而SERS分析显示，与纯Cu2O相比，银修饰的氧化亚铜的信号增强。在0.01 g的样品中获得了最佳条件，并将其用于合成Ag@Cu2O/p-Si异质结，以提高光电探测器的性能，包括响应率，探测率和量子效率。与纯Cu2O/p-Si相比，其内置电位为1.4 V。该设备的这种配置产生了在整个可见到近红外光谱的响应性增强。

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引用次数: 0

Mixed finite element method for device simulations 器件仿真的混合有限元法

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-06-01 Epub Date: 2026-01-30 DOI: 10.1016/j.sse.2026.109346

Yingjia Gao, Naveen Kumar, Ross Williams, Andrei Shvarts, Łukasz Kaczmarczyk, Vihar Georgiev

This paper presents a new numerical approach for simulating semiconductor devices using the Mixed Finite Element Method (Mixed FEM). Compared to the standard finite element method, Mixed FEM enables a more accurate treatment of material discontinuities, resulting in improved carrier density simulation across heterogeneous interfaces. Our main contribution is the implementation of Mixed FEM for semiconductor equations involving heterogeneous material interfaces, using the open-source, parallel finite element library MoFEM, thereby providing an extensible platform for future research. In particular, the Mixed FEM formulation results in a specific block-matrix structure that is compatible with GPU acceleration, paving the way for efficient large-scale device simulations.

本文提出了一种新的模拟半导体器件的数值方法——混合有限元法。与标准有限元方法相比，混合有限元法能够更精确地处理材料不连续，从而改善了跨异质界面的载流子密度模拟。我们的主要贡献是使用开源的并行有限元库MoFEM实现涉及异质材料界面的半导体方程的混合有限元，从而为未来的研究提供一个可扩展的平台。特别是，混合FEM公式产生了与GPU加速兼容的特定块矩阵结构，为高效的大规模设备模拟铺平了道路。

引用次数: 0

Assessment of dual-oxide options for LDMOS transistors in FinFET technology 在FinFET技术中LDMOS晶体管的双氧化物选择评估

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-06-01 Epub Date: 2026-02-04 DOI: 10.1016/j.sse.2026.109345

Alessandro Ruggieri, Lisa Tondelli, Luca Selmi

We present a comparison of three LDMOS transistor designs in

≃

16 nm FinFET technology with different gate stack configurations: thick ITL oxide, thin ITL oxide, and a combination of both (dual ITL oxide thickness). We analyze by simulation how the gate oxide stack influences the main performance and time-zero degradation rate indicators.

The simulations suggest that, for the same doping profile and gate length (L

_{G}

), the dual-oxide configuration has transition frequency (f

_{T}

) and on-resistance (R

_{DS,on}

) within

\approx

16% and 6% of those of thick and thin-oxide devices, respectively, while the maximum substrate and gate currents are

\approx

35% and 43% smaller than for a fully thin-oxide device, respectively. Consequently, the dual-oxide configuration enables L

_{G}

scaling and improvements in f

_{T}

and R

_{DS,on}

while keeping degradation monitors under control.

我们比较了三种具有不同栅极堆叠结构的LDMOS晶体管设计：厚的ITL氧化物，薄的ITL氧化物，以及两者的组合（双ITL氧化物厚度）。通过仿真分析了栅极氧化层对主要性能和时间零降解率指标的影响。模拟结果表明，在相同的掺杂谱线和栅极长度（LG）下，双氧化物结构的跃迁频率（fT）和导通电阻（RDS,on）分别在厚层和薄层氧化器件的约16%和6%以内，而最大衬底和栅极电流分别比完全薄层氧化器件小约35%和43%。因此，双氧化物结构可以实现LG缩放和改进fT和RDS，同时保持退化监视器处于控制之下。

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引用次数: 0

A probabilistic compact model of ReRAM memories for accurate and high-performance simulation 一个精确和高性能仿真的概率紧凑模型

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-06-01 Epub Date: 2026-02-05 DOI: 10.1016/j.sse.2026.109349

S. Guitarra, M. Gavilánez, J. Cevallos, A. Vélez

This work presents a compact, circuit-level model for resistive random-access memories (ReRAMs) that combines physical consistency with computational efficiency. Within a memristive framework, device history is explicitly captured through a state variable describing the cumulative evolution of the active region of the conductive filament. The filament transition region is modeled as a network of parallel stochastic conductive paths governed by voltage-dependent switching probabilities calibrated from experimental data, enabling accurate reproduction of intrinsic IV variability. Electrical transport is described using closed-form expressions that capture ohmic conduction in the low-resistance state and nonlinear behavior in the high-resistance state. The model is fully implemented in HSPICE and calibrated using HfO

_{2}

-based 1T1R devices. Circuit-level validation demonstrates accurate reproduction of electrical characteristics, variability, multilevel operation, and logic-in-memory functionality.

这项工作提出了一种紧凑的电路级电阻随机存取存储器（reram）模型，该模型结合了物理一致性和计算效率。在忆阻框架内，器件历史通过描述导电丝有源区域的累积演化的状态变量被明确捕获。灯丝过渡区被建模为由实验数据校准的电压相关开关概率控制的并行随机导电路径网络，从而能够精确再现固有的IV可变性。电输运是用封闭形式的表达式来描述的，它捕获了低电阻状态下的欧姆传导和高电阻状态下的非线性行为。该模型在HSPICE中完全实现，并使用基于hfo2的1T1R器件进行校准。电路级验证演示了电特性、可变性、多电平操作和内存逻辑功能的准确再现。

引用次数: 0

Impact of top electrode materials on resistive switching characteristics of TiOx-based MIM structures 顶电极材料对tiox基MIM结构阻性开关特性的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-04-01 Epub Date: 2026-01-01 DOI: 10.1016/j.sse.2025.109329

Karimul Islam , Rezwana Sultana , Aleksandra Dzięgielewska , Robert Mroczyński

This study investigates the influence of the top metal electrode on the resistive switching (RS) behavior of the metal/TiO_x/ITO structure. Specifically, the effects of Al and TiN as top electrodes were examined in devices utilizing a 30 nm TiO_x thin film as the active layer, deposited using a pulsed-DC reactive sputtering technique. Both configurations exhibited non-volatile bipolar resistive switching, demonstrating endurance over 100 cycles and stable data retention (>10⁴ s). The results indicate that the choice of top electrode (TE) plays a crucial role in determining the electroforming process, current conduction mechanisms, and overall RS performance. Notably, devices with TiN as a TE exhibited more consistent RS behavior, with a superior ON/OFF ratio and enhanced operational stability. These findings demonstrate that electrode engineering offers a viable pathway to enhance resistive switching performance. The insights gained from this study provide a basis for the rational design and optimization of CMOS-compatible TiO_x-based resistive random-access memory (RRAM) devices.

本文研究了顶部金属电极对金属/TiOx/ITO结构电阻性开关（RS）行为的影响。具体来说，使用脉冲直流反应溅射技术沉积的30 nm TiOx薄膜作为活性层，在器件中测试了Al和TiN作为顶电极的效果。这两种配置都具有非易失性双极电阻开关，具有超过100次循环的耐久性和稳定的数据保留（104秒）。结果表明，顶电极（TE）的选择对电铸工艺、电流传导机制和整体RS性能起着至关重要的作用。值得注意的是，以TiN为TE的器件表现出更一致的RS行为，具有优越的开/关比和增强的工作稳定性。这些发现表明，电极工程为提高电阻开关性能提供了一条可行的途径。本研究为合理设计和优化cmos兼容的tiox型电阻随机存取存储器（RRAM）器件提供了基础。

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引用次数: 0

A 10T2R non-volatile SRAM cell design with high-reliability 一种高可靠性的10T2R非易失性SRAM单元设计

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-04-01 Epub Date: 2025-12-05 DOI: 10.1016/j.sse.2025.109304

So-Yeon Kwon, Woon-San Ko, Jun-Ho Byun, Do-Yeon Lee, So-Yeong Park, Hye-Ri Hong, Ga-Won Lee

In this study, a highly reliable 10T2R non-volatile SRAM (nvSRAM) cell is proposed. The previous nvSRAM structures face reliability issues of Resistive Random-Access Memory (RRAM) due to unwanted stress-induced data nodes. To overcome this challenge, the proposed 10T2R nvSRAM design integrates two transistors that effectively isolate both ends of the RRAM, acting as voltage blockers and current controllers. The SPICE simulation results show that the voltage stress applied to the RRAM during the Read/Write operation is less than 1 mV. Regarding the static noise margin (SNM), the SNM value of the 10T2R in each operation is similar to that of a 6T SRAM. Additionally, it successfully performs the RESTORE operation after power-on and demonstrates low power consumption. This highlights the potential of the proposed 10T2R cell to advance non-volatile memory technology.

在这项研究中，提出了一个高可靠的10T2R非易失性SRAM （nvSRAM）单元。以前的nvSRAM结构由于不需要应力引起的数据节点而面临电阻随机存取存储器（RRAM）的可靠性问题。为了克服这一挑战，提出的10T2R nvSRAM设计集成了两个晶体管，有效地隔离了RRAM的两端，作为电压阻滞器和电流控制器。SPICE仿真结果表明，读写过程中施加在RRAM上的电压应力小于1 mV。关于静态噪声裕度（SNM）， 10T2R在每次操作中的SNM值与6T SRAM相似。开机后能成功执行RESTORE操作，功耗低。这突出了所提出的10T2R电池在推进非易失性存储技术方面的潜力。

引用次数: 0

Warm white electrical sensitivities of pentacene-based Schottky photodiode 五苯基肖特基光电二极管的暖白色电灵敏度

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-04-01 Epub Date: 2025-12-29 DOI: 10.1016/j.sse.2025.109327

Ghusoon M. Ali , Kahtan Adnan Hussain , Shahad T. Armoot

This study investigates the electrical sensitivities of warm white Al/pentacene/p-Si/Pd Schottky photodiodes with respect to current–voltage (I-V), capacitance–voltage (C-V), and conductance-voltage (G-V) characteristics. The pentacene thin film is deposited using the vacuum thermal evaporation technique. The energy level parameters of the Schottky junction are estimated through energy band diagrams. Two models are introduced to analyze the forward I-V characteristics of the pentacene Schottky diode: the thermionic emission theory and the space-charge-limited current model, both of which explain the mechanisms of charge carrier transport. The I-V, C-V, and G-V characteristics were examined under both dark and warm white illumination conditions, across a voltage range of −4 to 4 V at room temperature. Moreover, a study was conducted to assess, extract, and compare the sensitivities of current (S_I), capacitance (S_C), and conductance (S_CO). The maximum S_I is 1682 % at 0 V. Therefore, the proposed device demonstrates outstanding performance as a self-powered photodetector. The maximum S_C is 38 % at −2.1 V, and S_CO is 370 % at −1.6 V. The variations in sensitivity values are attributed to the different detection mechanisms employed. Overall, the results demonstrate the significant potential of the current-mode Schottky pentacene diode for use as a warm white self-powered photodetector.

本研究考察了暖白色Al/pentacene/p-Si/Pd肖特基光电二极管在电流电压（I-V）、电容电压（C-V）和电导电压（G-V）特性方面的电灵敏度。采用真空热蒸发技术制备了并五苯薄膜。利用能带图估计了肖特基结的能级参数。引入了热离子发射理论和空间电荷限制电流模型两种模型来分析并苯肖特基二极管的正向I-V特性，这两种模型都解释了载流子输运的机理。在室温下，在−4到4 V的电压范围内，在黑暗和温暖的白色照明条件下，研究了I-V、C-V和G-V特性。此外，还进行了一项研究，以评估、提取和比较电流（SI）、电容（SC）和电导（SCO）的灵敏度。在0 V时，最大SI为1682 %。因此，所提出的器件表现出作为自供电光电探测器的出色性能。在−2.1 V时最大SC为38 %，在−1.6 V时最大SCO为370 %。灵敏度值的变化归因于所采用的不同检测机制。总的来说，结果证明了电流模式肖特基五苯二极管作为暖白色自供电光电探测器的巨大潜力。

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引用次数: 0

Exploring low-k/high-k multilayers as high breakdown strength dielectrics for capacitors 探索低钾/高钾多层电容器的高击穿强度介质

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2026-04-01 Epub Date: 2026-01-15 DOI: 10.1016/j.sse.2026.109331

Julie Chaussard , Chloé Guérin , Aude Lefèvre , Patrice Gonon , Vincent Jousseaume

In this work, low-k/high-k multilayers were developed to improve the electrical performance of capacitors in high-voltage applications. SiOCH/HfO₂ stacks were deposited by PECVD and ALD at 300°C on 200 mm Si wafers achieving a total thickness of around 115 nm, with variations in the number of layers and the capacitor area. The results show that the dielectric layers are continuous and of good quality. Using the multilayer approach of alternating SiOCH and HfO₂ layers, the dielectric constant and breakdown strength are significantly improved compared to a single SiOCH layer, without degrading the dielectric losses. This strategy seems promising for high-voltage capacitors.

在这项工作中，开发了低k/高k多层材料，以改善高压应用中电容器的电性能。SiOCH/HfO2堆栈通过PECVD和ALD在300°C下沉积在200 mm Si晶圆上，总厚度约为115 nm，层数和电容器面积有所变化。结果表明，介质层连续且质量良好。使用SiOCH和HfO2交替的多层方法，与单一SiOCH层相比，介电常数和击穿强度显着提高，而介电损耗不降低。这种策略对于高压电容器似乎很有希望。

引用次数: 0

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