Triple-metal gate work function engineering to improve the performance of junctionless cylindrical gate-all-around Si nanowire MOSFETs for the upcoming sub-3-nm technology node

Abstract

Moore’s law, along with the International Roadmap for Devices and Systems, continues to guide the scaling of devices below 10 nm. The challenges posed by such small-dimensioned devices form the basis of the present work. A junctionless MOSFET with a triple-metal gate structure is proposed as an alternative to conventional single-gate bulk MOSFETs for future CMOS technology. The present work investigated the direct current and analog/radio frequency characteristics including the drain current \(({I}_{{\text{D}}}\)), transconductance \({(g}_{m})\), transconductance generation factor (TGF), cut-off frequency \({(f}_{T})\), frequency–transconductance product (FTP), transit time \((\tau ),\) and the total resistance of the source region, drain region, and channel \({(R}_{{\text{SD}}+{\text{CH}}})\) for triple-metal (TM) inversion-mode (IM) and junctionless (JL) cylindrical gate-all-around (CGAA) silicon nanowire (SiNW) MOSFETs with 3-nm gate length using the Silvaco ATLAS 3D TCAD tool. The non-equilibrium Green’s function and the self-consistent solution of the Schrödinger and Poisson equations were considered. The channel was taken to be lightly doped in the case of the IM TM CGAA SiNW device. The effect of the TM gate work function engineering for a SiNW channel with a diameter of 3 nm and gate oxide \(({{{\text{Al}}}_{2}{\text{O}}}_{3})\) thickness of 0.8 nm was investigated with respect to \({I}_{D}\),\({ g}_{m}\), TGF, \({f}_{T}\), \(\tau\), FTP, and \({R}_{{\text{SD}}+{\text{CH}}}\), and a comparative study between the IM TM and JL TM CGAA SiNW devices was carried out with respect to these parameters. For the JL device, optimization of the doping concentration was performed to obtain the same (i) I_ON current and (ii) threshold voltage (V_TH) as the IM device. An 8.61- and 5.72-fold reduction in I_OFF was seen for the same I_ON and V_TH for the JL versus the IM device. It was found that the TM gate variation led to a reduction in drain-induced barrier lowering (DIBL) in the IM and JL devices. The JL SiNW showed much lower DIBL of ~39.49 mV/V, a near-ideal subthreshold slope (SS) of ~60 mV/dec, and higher \({{\text{I}}}_{{\text{ON}}}/{{\text{I}}}_{{\text{OFF}}}\) current ratio of ~2.98 × 10¹². which is much better than the values reported in the literature for CGAA devices. Also, the JL SiNW device was found to perform better than the IM SiNW device in terms of SS, DIBL, \({{\text{I}}}_{{\text{ON}}}/{{\text{I}}}_{{\text{OFF}}}\), \({g}_{m},\) TGF, f_T, \(\tau\), FTP, and \({R}_{{\text{SD}}+{\text{CH}}}\).