Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

Abstract

This work explores the characteristics of ferroelectric thin-film transistors (FeTFTs) utilizing an asymmetric dual-gate (DG) structure in both single-gate (SG) and DG operation modes. In the transfer characteristics, DG mode exhibits a memory window (MW) of 1.075 V, smaller than SG mode’s MW of 1.402 V, attributed to the back-gate bias effect causing a reduction in the device’s threshold voltage. However, DG mode demonstrates superior endurance characteristics with 10⁶ cycles compared to SG mode’s 10⁵ cycles. Additionally, the increase in erase pulse voltage (V_ERS) exacerbates the polycrystalline-silicon channel lattice damage of FeTFT, resulting in subthreshold swing (SS) degradation. Nevertheless, the extent of SS degradation from DG mode operation is significantly lower than that of SG mode, contributing to the superior endurance of DG mode. The elevation of program pulse voltage (V_PRG) induces imprint and charge-trapping effects in the top-gate ferroelectric dielectric, leading to reduced endurance. Due to the use of SiO₂ as the back-gate dielectric in FeTFT, DG mode exhibits lower impacts of charge-trapping effects from the top-gate ferroelectric dielectric layer, resulting in better endurance compared to SG mode. The asymmetric DG structure provides greater tolerance in the selection of V_PRG and V_ERS.