Theoretical and simulation-based assessment of electrically doped junctionless TFET with metal-strip and hetero-material considering interface trap charges

Abstract

The fabrication complexity, ambipolar current conduction ($I_{ambi}$), inferior ON-state current ($I_{on}$), and poor analog/RF performance are major limitations of conventional tunnel field-effect transistors (TFETs). To address these challenges, we propose a novel approach utilizing hetero-material (HM) and metal-strip (MS) technology to develop an electrically doped junctionless TFET (HM-MS-ED-JL-TFET). Utilizing work function engineering (4.72 eV) at the control gate (CG) establishes an intrinsic region along the channel, while a combination of work function engineering (4.72 eV) and a polarity bias (electrically doped) of PG = -1.2 V at the polarity gate (PG) induces a $P^{+}$ region across the source, forming an $N^{+}$-i-$P^{+}$ structure over the thin $N^{+}$-$N^{+}$-$N^{+}$ silicon body. This approach effectively mitigates concerns regarding random dopant fluctuations (RDF) without necessitating a thermal budget, streamlining fabrication compared to conventional TFETs. Furthermore, the integration of hetero-material into the source region narrows the tunneling barrier width, enhancing band-to-band tunneling at the source-channel interface and improving critical metrics such as ON-state current ($I_{on}$), subthreshold slope (SS), transconductance ($g_m$), and cut-off frequency ($f_T$). Concurrently, the inclusion of a metal strip at the drain-channel region raises the energy band and suppresses the ambipolar current. To optimize device performance, a comprehensive optimization phase involving material selection, length, and work function tuning of the metal strip is incorporated. Additionally, reliability concerns arising from interface trap charges (ITCs) at the oxide-semiconductor interface during fabrication are investigated. Through extensive simulations utilizing the Silvaco ATLAS device simulator, we demonstrate the enhanced immunity of the HM-MS-ED-JLTFET to various ITCs, rendering it more reliable for ultra-low-power and high-frequency applications compared to conventional counterparts like ED-JLTFET and MS-ED-JLTFET.