This paper reports a demonstration of a new sensor device structure designed to increase the current change for detecting power cycle degradation. In a previous study, a low-cost and high-accuracy sensor device was proposed, which can be integrated into power device chip. The sensor device consists of a Schottky barrier MISFET. Power cycling degradation is detected by a decrease in the drain current of the SB-MISFET, as repetitive mechanical stress increases the interface state density of the MIS gate. The sensor devices demonstrated the basic operation of a decrease in drain current due to repetitive mechanical stress. However, the change in current was only 4 to 5 times smaller than initial current. In this study, it is clarified that this current change is limited by leakage current, and a new structure is proposed to suppress this leakage current. The proposed structure achieved a current change 12 to 13 times smaller than the initial current, due to the leakage current 1/8 times smaller compared to the conventional structure.
{"title":"Improvement of sensitivity for power cycle degradation by a new device structure","authors":"Koki Okame , Yuki Yamakita , Shin-ichi Nishizawa , Wataru Saito","doi":"10.1016/j.microrel.2025.115713","DOIUrl":"10.1016/j.microrel.2025.115713","url":null,"abstract":"<div><div>This paper reports a demonstration of a new sensor device structure designed to increase the current change for detecting power cycle degradation. In a previous study, a low-cost and high-accuracy sensor device was proposed, which can be integrated into power device chip. The sensor device consists of a Schottky barrier MISFET. Power cycling degradation is detected by a decrease in the drain current of the SB-MISFET, as repetitive mechanical stress increases the interface state density of the MIS gate. The sensor devices demonstrated the basic operation of a decrease in drain current due to repetitive mechanical stress. However, the change in current was only 4 to 5 times smaller than initial current. In this study, it is clarified that this current change is limited by leakage current, and a new structure is proposed to suppress this leakage current. The proposed structure achieved a current change 12 to 13 times smaller than the initial current, due to the leakage current 1/8 times smaller compared to the conventional structure.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115713"},"PeriodicalIF":1.6,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143760922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-02DOI: 10.1016/j.microrel.2025.115720
Bin Yu , Xingjian Shi , Haoze Luo , Wenbo Wang , Zhiwen Chen , Min Zhang , Francesco Iannuzzo , Wuhua Li
In this paper, the electro-thermal-mechanical stress of SiC MOSFETs under current-limited short circuit (CL-SC) conditions, as employed in DC solid-state power controllers (DC-SSPCs), is investigated. The low on-resistance and high operating junction temperature (TJ) characteristics of SiC MOSFETs make them ideal power devices for DC-SSPC applications. During the clearing of a short circuit fault, the short circuit current is limited to a lower value by the DC-SSPC for an extended duration before being cut off. This leads to an increase in TJ within the SiC MOSFET, which raises reliability concerns. Research on the short circuit (SC) reliability of SiC MOSFETs has predominantly focused on the electro-thermal-mechanical stress under SC conditions in high-frequency converters (HFCs). However, the electro-thermal-mechanical stress and aging mechanisms of SiC MOSFETs under CL-SC conditions remain unclear. In this paper, SPICE-based and FEM-based simulations are conducted to analyze the electro-thermal-mechanical stress of SiC MOSFETs under CL-SC for DC-SSPCs and SC for HFCs. Results indicate that bonding wire lift-off, edge delamination, and voids in the middle of the solder layer are more likely to occur under CL-SC conditions, differing from those observed in SC for HFCs. Experimental results are presented to validate the simulation findings, providing a valuable reference for evaluating the reliability of SiC MOSFETs in DC-SSPC applications.
{"title":"Comparison of electro-thermal-mechanical stress in SiC MOSFETs under several short-circuit types","authors":"Bin Yu , Xingjian Shi , Haoze Luo , Wenbo Wang , Zhiwen Chen , Min Zhang , Francesco Iannuzzo , Wuhua Li","doi":"10.1016/j.microrel.2025.115720","DOIUrl":"10.1016/j.microrel.2025.115720","url":null,"abstract":"<div><div>In this paper, the electro-thermal-mechanical stress of SiC MOSFETs under current-limited short circuit (CL-SC) conditions, as employed in DC solid-state power controllers (DC-SSPCs), is investigated. The low on-resistance and high operating junction temperature (<em>T</em><sub><em>J</em></sub>) characteristics of SiC MOSFETs make them ideal power devices for DC-SSPC applications. During the clearing of a short circuit fault, the short circuit current is limited to a lower value by the DC-SSPC for an extended duration before being cut off. This leads to an increase in <em>T</em><sub><em>J</em></sub> within the SiC MOSFET, which raises reliability concerns. Research on the short circuit (SC) reliability of SiC MOSFETs has predominantly focused on the electro-thermal-mechanical stress under SC conditions in high-frequency converters (HFCs). However, the electro-thermal-mechanical stress and aging mechanisms of SiC MOSFETs under CL-SC conditions remain unclear. In this paper, SPICE-based and FEM-based simulations are conducted to analyze the electro-thermal-mechanical stress of SiC MOSFETs under CL-SC for DC-SSPCs and SC for HFCs. Results indicate that bonding wire lift-off, edge delamination, and voids in the middle of the solder layer are more likely to occur under CL-SC conditions, differing from those observed in SC for HFCs. Experimental results are presented to validate the simulation findings, providing a valuable reference for evaluating the reliability of SiC MOSFETs in DC-SSPC applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115720"},"PeriodicalIF":1.6,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-01DOI: 10.1016/j.microrel.2025.115725
Myong Hun Oh , Su Hyun Yoon , Soo Il Jeon , Minsuk Choi
Effective thermal management of automotive radar sensors operating under natural convection is essential for their optimal performance and reliability. This study introduces a comprehensive thermal design methodology for an automotive radar sensor using both experimental measurements and numerical simulations. Major heat-generating components in the radar sensor were firstly identified, and their temperatures were measured to determine the heat generation rates. Numerical simulations were then conducted to model the sensor's thermal behavior with and without its enclosure, focusing on natural convection as the primary cooling mechanism. Various thermal design strategies, including thermal bridges, were tested to improve the sensor's cooling. Experimental results demonstrated that the proposed methodology could increase the duty cycle of the radar sensor by approximately 6 % at room temperature and 8 % at high temperatures. This research highlights the effectiveness of the proposed thermal design methodology in addressing thermal management challenges, thereby improving the performance and reliability of automotive radar sensors in confined spaces.
{"title":"Thermal management of automotive radar: Overcoming design challenges in constrained environments","authors":"Myong Hun Oh , Su Hyun Yoon , Soo Il Jeon , Minsuk Choi","doi":"10.1016/j.microrel.2025.115725","DOIUrl":"10.1016/j.microrel.2025.115725","url":null,"abstract":"<div><div>Effective thermal management of automotive radar sensors operating under natural convection is essential for their optimal performance and reliability. This study introduces a comprehensive thermal design methodology for an automotive radar sensor using both experimental measurements and numerical simulations. Major heat-generating components in the radar sensor were firstly identified, and their temperatures were measured to determine the heat generation rates. Numerical simulations were then conducted to model the sensor's thermal behavior with and without its enclosure, focusing on natural convection as the primary cooling mechanism. Various thermal design strategies, including thermal bridges, were tested to improve the sensor's cooling. Experimental results demonstrated that the proposed methodology could increase the duty cycle of the radar sensor by approximately 6 % at room temperature and 8 % at high temperatures. This research highlights the effectiveness of the proposed thermal design methodology in addressing thermal management challenges, thereby improving the performance and reliability of automotive radar sensors in confined spaces.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115725"},"PeriodicalIF":1.6,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-01DOI: 10.1016/j.microrel.2025.115718
M. Dammann , P. Brückner , R. Driad , S. Krause , S.A. Albahrani , B. Weber , M. Baeumler , H. Konstanzer , M. Mikulla , M. Simon-Najasek , S. Hübner , A. Graff
By comparing the reliability of 150 nm AlGaN/GaN HEMTs with PtAu gates to devices with NiPtAu SiN assisted gates, it was found that PtAu gates are more stable in terms of gate leakage current increase under HTRB step stress test and show smaller spread of the extrapolated lifetime values during long-term DC stress tests. An activation energy of 1.39 eV (1.97 eV) and a lifetime of around 107 h at Tch = 175 °C and Vd = 30 V has been extrapolated for devices with PtAu (NiPtAu) SiN assisted gate. By TEM cross sectioning and EDX mapping analysis of aged devices, the degradation of NiPtAu gate devices was attributed to a stress-induced local oxidation of the SiN passivation on the drain side of the gate foot. An activation energy of 1.15 eV and a lifetime of 5 · 104 h at Tch = 175 °C and Vd = 15 V has been extrapolated for devices with 100 nm T-gate reference technology. The faster degradation of the T-gate is possibly caused by a higher lateral electric field at the gate foot. T-gate reference technology lifetime is increased by more than an order of magnitude by reducing the drain voltage to 10 V.
{"title":"Reliability and failure analysis of AlGaN/GaN HEMT with NiPtAu and PtAu gate","authors":"M. Dammann , P. Brückner , R. Driad , S. Krause , S.A. Albahrani , B. Weber , M. Baeumler , H. Konstanzer , M. Mikulla , M. Simon-Najasek , S. Hübner , A. Graff","doi":"10.1016/j.microrel.2025.115718","DOIUrl":"10.1016/j.microrel.2025.115718","url":null,"abstract":"<div><div>By comparing the reliability of 150 nm AlGaN/GaN HEMTs with PtAu gates to devices with NiPtAu SiN assisted gates, it was found that PtAu gates are more stable in terms of gate leakage current increase under HTRB step stress test and show smaller spread of the extrapolated lifetime values during long-term DC stress tests. An activation energy of 1.39 eV (1.97 eV) and a lifetime of around 10<sup>7</sup> h at T<sub>ch</sub> = 175 °C and V<sub>d</sub> = 30 V has been extrapolated for devices with PtAu (NiPtAu) SiN assisted gate. By TEM cross sectioning and EDX mapping analysis of aged devices, the degradation of NiPtAu gate devices was attributed to a stress-induced local oxidation of the SiN passivation on the drain side of the gate foot. An activation energy of 1.15 eV and a lifetime of 5 · 10<sup>4</sup> h at T<sub>ch</sub> = 175 °C and V<sub>d</sub> = 15 V has been extrapolated for devices with 100 nm T-gate reference technology. The faster degradation of the T-gate is possibly caused by a higher lateral electric field at the gate foot. T-gate reference technology lifetime is increased by more than an order of magnitude by reducing the drain voltage to 10 V.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115718"},"PeriodicalIF":1.6,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143737851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nowadays, the increasing tendency towards the exploitation of solar energy has yielded many technological advancements. Hybrid approaches are attracting attention worldwide to ensure the comprehensive assessment of photovoltaic modules reliability becoming a crucial issue. The present study is dedicated to the investigation of an innovative approach integrating Bond graph theory, Gaussian mixture models and Similarity-based method for fault detection and remaining useful life prediction. In this context, Bond graphs are exploited first to create a dataset covering diverse operational modes of the system. The identification and evaluation of critical sensors for fault observability is also considered, where the dataset is optimized based on the variance analysis. The Gaussian mixture model with its semi-supervised initialization is then utilized for clustering and fault diagnosis, while remaining useful life estimation is performed using a pairwise similarity technique. Validation results on a photovoltaic panel model demonstrate that the Gaussian mixture model consistently outperforms the classical k-Nearest Neighbors model across all key metrics (accuracy of 0.9396 vs. 0.7577, precision of 0.9192 vs. 0.5570, recall of 0.7849 vs. 0.5628, and F1-score of 0.8666 vs. 0.6707), highlighting its superior performance. The remaining useful lifetime model also achieves high accuracy, with Root Mean Square Error values ranging from 0.0282 to 0.0300, indicating minimal prediction error. Additionally, the R-Squared value of ~0.92 shows that the model explains approximately 92% of the variance in remaining useful lifetime predictions, underscoring its strong predictive capability. The results demonstrate the practical effectiveness of the proposed framework for both single and multiple faults. However, some limitations are noted, such as the exclusion of the transition phase in training data and the reliance on controlled conditions. The outcomes of this work are expected to provide valuable insights into the implementation of efficient hybrid frameworks, contributing to the sustainable development of solar energy.
{"title":"An integrated physical model and extant data based approach for fault diagnosis and failure prognosis: Application to a photovoltaic module","authors":"Nassima Mebarki , Leïla-Hayet Mouss , Toufik Bentrcia , Samir Benmoussa","doi":"10.1016/j.microrel.2025.115711","DOIUrl":"10.1016/j.microrel.2025.115711","url":null,"abstract":"<div><div>Nowadays, the increasing tendency towards the exploitation of solar energy has yielded many technological advancements. Hybrid approaches are attracting attention worldwide to ensure the comprehensive assessment of photovoltaic modules reliability becoming a crucial issue. The present study is dedicated to the investigation of an innovative approach integrating Bond graph theory, Gaussian mixture models and Similarity-based method for fault detection and remaining useful life prediction. In this context, Bond graphs are exploited first to create a dataset covering diverse operational modes of the system. The identification and evaluation of critical sensors for fault observability is also considered, where the dataset is optimized based on the variance analysis. The Gaussian mixture model with its semi-supervised initialization is then utilized for clustering and fault diagnosis, while remaining useful life estimation is performed using a pairwise similarity technique. Validation results on a photovoltaic panel model demonstrate that the Gaussian mixture model consistently outperforms the classical k-Nearest Neighbors model across all key metrics (accuracy of 0.9396 vs. 0.7577, precision of 0.9192 vs. 0.5570, recall of 0.7849 vs. 0.5628, and F1-score of 0.8666 vs. 0.6707), highlighting its superior performance. The remaining useful lifetime model also achieves high accuracy, with Root Mean Square Error values ranging from 0.0282 to 0.0300, indicating minimal prediction error. Additionally, the R-Squared value of ~0.92 shows that the model explains approximately 92% of the variance in remaining useful lifetime predictions, underscoring its strong predictive capability. The results demonstrate the practical effectiveness of the proposed framework for both single and multiple faults. However, some limitations are noted, such as the exclusion of the transition phase in training data and the reliance on controlled conditions. The outcomes of this work are expected to provide valuable insights into the implementation of efficient hybrid frameworks, contributing to the sustainable development of solar energy.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115711"},"PeriodicalIF":1.6,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-01DOI: 10.1016/j.microrel.2025.115723
F. Velardi , G. Canale Parola , S. Palazzo , E. Martano , A. Sanseverino , L. Silvestrin , C. Abbate , G. Busatto
The behaviour of a 350 V Enhancement Mode GaN power HEMT during heavy ion irradiation is presented. A new experimental setup has been developed to increase the sensitivity of the measurement. It allowed the measurement of the charge collected at the terminals following the impact with energetic particles to be extended by almost an order of magnitude. The results obtained, interpreted with the help of two-dimensional finite element simulations, demonstrate that the tested devices exhibit very different behaviour from those previously characterized. They do not show significant charge amplification and are not subjected to single-event gate rupture. Furthermore, it is demonstrated that the device failure is due to a recursive mechanism like that which develops in silicon PiN diodes when exposed to heavy ion irradiation.
{"title":"The behaviour of 350 V GaN HEMTs during heavy ion irradiations","authors":"F. Velardi , G. Canale Parola , S. Palazzo , E. Martano , A. Sanseverino , L. Silvestrin , C. Abbate , G. Busatto","doi":"10.1016/j.microrel.2025.115723","DOIUrl":"10.1016/j.microrel.2025.115723","url":null,"abstract":"<div><div>The behaviour of a 350 V Enhancement Mode GaN power HEMT during heavy ion irradiation is presented. A new experimental setup has been developed to increase the sensitivity of the measurement. It allowed the measurement of the charge collected at the terminals following the impact with energetic particles to be extended by almost an order of magnitude. The results obtained, interpreted with the help of two-dimensional finite element simulations, demonstrate that the tested devices exhibit very different behaviour from those previously characterized. They do not show significant charge amplification and are not subjected to single-event gate rupture. Furthermore, it is demonstrated that the device failure is due to a recursive mechanism like that which develops in silicon PiN diodes when exposed to heavy ion irradiation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115723"},"PeriodicalIF":1.6,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-31DOI: 10.1016/j.microrel.2025.115714
S.L. Longato , D. Favero , A. Stockman , A. Nardo , P. Vanmeerbeek , M. Tack , G. Meneghesso , E. Zanoni , C. De Santi , M. Meneghini
We present an extensive analysis of the impact of drain-source off-state leakage current on the dynamic on-resistance of GaN HEMTs with p-GaN gate. We analyzed two wafers with epitaxial layers grown under different conditions. The difference in the epitaxial layers gives an impact on the off-state leakage. We analyzed all the leakage components demonstrating that the wafer with lower off-state leakage shows a large dynamic Ron instability. Based on current transient measurements performed in temperature, this difference is explained by considering that a larger leakage (still below the nA) through the unintentionally-doped channel layer can ease the generation of positive charge at the bottom of the buffer, with consequent compensation of the dynamic Ron effect. The methodology presented in this paper constitutes a rapid and effective approach to evaluate the conductivity of the GaN channel layer, and its contribution to device stability.
{"title":"Impact of drain-source leakage on the dynamic Ron of power HEMTs with p-GaN gate","authors":"S.L. Longato , D. Favero , A. Stockman , A. Nardo , P. Vanmeerbeek , M. Tack , G. Meneghesso , E. Zanoni , C. De Santi , M. Meneghini","doi":"10.1016/j.microrel.2025.115714","DOIUrl":"10.1016/j.microrel.2025.115714","url":null,"abstract":"<div><div>We present an extensive analysis of the impact of drain-source off-state leakage current on the dynamic on-resistance of GaN HEMTs with p-GaN gate. We analyzed two wafers with epitaxial layers grown under different conditions. The difference in the epitaxial layers gives an impact on the off-state leakage. We analyzed all the leakage components demonstrating that the wafer with lower off-state leakage shows a large dynamic R<sub>on</sub> instability. Based on current transient measurements performed in temperature, this difference is explained by considering that a larger leakage (still below the nA) through the unintentionally-doped channel layer can ease the generation of positive charge at the bottom of the buffer, with consequent compensation of the dynamic R<sub>on</sub> effect. The methodology presented in this paper constitutes a rapid and effective approach to evaluate the conductivity of the GaN channel layer, and its contribution to device stability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115714"},"PeriodicalIF":1.6,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143737845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-31DOI: 10.1016/j.microrel.2025.115719
YehRi Kim , Eunjin Jo , Byeong Kwon Ju , Yoongul Lee , Jaeup Kim , Kijoon Ahn , Seungjun Noh , Dongjin Kim
This study was carried out to understand the high-temperature stability of Ag nano-porous sheet bonded joints during thermal aging. The joints have been designed to be between two Ag metallization layers directly plated on copper layers of the die and substrate. The CuxO penetration between Ag plated layer and Cu substrate formed during thermal aging at 250 °C from 125 h, during which CuxO layer continuously grew up to 1000 h. The growing CuxO phase penetrated between the Ag plating and Cu, leading to voids that developed into a delamination layer over time. The delamination and continuous voids formed between CuxO layer and Cu had a critical effect on reducing the bonding strength. In this study, we thoroughly investigated the issues that may arise during thermal reliability testing at 250 °C when bonding commercial Ag nano-porous sheets directly Ag-plated onto Cu, from the perspective of microstructural development.
{"title":"Risk of CuxO phase penetration between the Ag plating layer and Cu during high-temperature reliability testing of interfaces bonded to cold sintered Ag nano-porous sheets on direct Ag-plated Cu substrates","authors":"YehRi Kim , Eunjin Jo , Byeong Kwon Ju , Yoongul Lee , Jaeup Kim , Kijoon Ahn , Seungjun Noh , Dongjin Kim","doi":"10.1016/j.microrel.2025.115719","DOIUrl":"10.1016/j.microrel.2025.115719","url":null,"abstract":"<div><div>This study was carried out to understand the high-temperature stability of Ag nano-porous sheet bonded joints during thermal aging. The joints have been designed to be between two Ag metallization layers directly plated on copper layers of the die and substrate. The Cu<sub>x</sub>O penetration between Ag plated layer and Cu substrate formed during thermal aging at 250 °C from 125 h, during which Cu<sub>x</sub>O layer continuously grew up to 1000 h. The growing Cu<sub>x</sub>O phase penetrated between the Ag plating and Cu, leading to voids that developed into a delamination layer over time. The delamination and continuous voids formed between Cu<sub>x</sub>O layer and Cu had a critical effect on reducing the bonding strength. In this study, we thoroughly investigated the issues that may arise during thermal reliability testing at 250 °C when bonding commercial Ag nano-porous sheets directly Ag-plated onto Cu, from the perspective of microstructural development.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115719"},"PeriodicalIF":1.6,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143737847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-31DOI: 10.1016/j.microrel.2025.115721
Le Xu , Yuyao Zhao , Shujuan Wang , Ji Jiang
Electrical connectors are important components in electrical systems, responsible for the transmission and control of electrical signals. In the process of use, frictional wear occurs between the pins and sockets of the contactor in an electrical connector. This phenomenon results in an increase in contact resistance, which can further lead to system failures, so it is critical to ensure the stability of the performance of the contactor. In this paper, a commonly used specification of wire-spring contacts is investigated. Firstly, the mechanical properties of the component were analyzed. Subsequently, the contact component underwent vibration testing under various conditions at room temperature to identify the wear patterns associated with different vibration scenarios. Finally, using the experimental data, a physical model of frictional wear failure was developed for the contact component, enabling the determination of contact failure time as a function of vibration amplitude and frequency.
{"title":"Research on the degradation of contact resistance of wire-spring contacts in different wear condition","authors":"Le Xu , Yuyao Zhao , Shujuan Wang , Ji Jiang","doi":"10.1016/j.microrel.2025.115721","DOIUrl":"10.1016/j.microrel.2025.115721","url":null,"abstract":"<div><div>Electrical connectors are important components in electrical systems, responsible for the transmission and control of electrical signals. In the process of use, frictional wear occurs between the pins and sockets of the contactor in an electrical connector. This phenomenon results in an increase in contact resistance, which can further lead to system failures, so it is critical to ensure the stability of the performance of the contactor. In this paper, a commonly used specification of wire-spring contacts is investigated. Firstly, the mechanical properties of the component were analyzed. Subsequently, the contact component underwent vibration testing under various conditions at room temperature to identify the wear patterns associated with different vibration scenarios. Finally, using the experimental data, a physical model of frictional wear failure was developed for the contact component, enabling the determination of contact failure time as a function of vibration amplitude and frequency.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115721"},"PeriodicalIF":1.6,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143737846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-30DOI: 10.1016/j.microrel.2025.115693
Michael Waltl , Konstantinos Tselios , Theresia Knobloch , Dominic Waldhoer , Hubert Enichlmair , Eleftherios G. Ioannidis , Rainer Minixhofer , Tibor Grasser
The performance of semiconductor transistors is significantly influenced by charge trapping at oxide and interface defects. The impact of charge-trapping events of defects on the characteristics of the transistor is strongly dependent on factors such as the geometry and the operating point at which the transistor is used. Understanding the complex relationships between the influence of defects and the robustness of devices is essential to optimize circuit performance and becomes particularly important in analog designs. In this work, we investigate the influence of gate oxide defects on the reliability of nanoscale MOS transistors under varying body bias conditions. Using measure-stress-measure techniques, we observe notable effects on both time-zero and time-dependent variability with the application of body bias. Furthermore, the amplitudes of the step heights are investigated as they provide an important measure in scaled technologies to estimate the impact of traps on the device behavior. The results indicate that a body bias can be strategically employed to enhance device reliability by fine-tuning the body bias conditions.
半导体晶体管的性能受氧化物和界面缺陷的电荷捕获影响很大。缺陷的电荷捕获事件对晶体管特性的影响与晶体管的几何形状和工作点等因素密切相关。了解缺陷影响与器件稳健性之间的复杂关系对于优化电路性能至关重要，在模拟设计中尤为重要。在这项工作中，我们研究了栅极氧化物缺陷在不同体偏压条件下对纳米级 MOS 晶体管可靠性的影响。利用测量-应力-测量技术，我们观察到施加体偏压对时间零点和随时间变化的显著影响。此外，我们还对阶跃高度的振幅进行了研究，因为在按比例放大技术中，阶跃高度是估算陷波对器件行为影响的重要指标。结果表明，可以有策略地使用体偏压，通过微调体偏压条件来提高器件的可靠性。
{"title":"Evaluation of the impact of body bias on the threshold voltage drift of planar SiO2 transistors","authors":"Michael Waltl , Konstantinos Tselios , Theresia Knobloch , Dominic Waldhoer , Hubert Enichlmair , Eleftherios G. Ioannidis , Rainer Minixhofer , Tibor Grasser","doi":"10.1016/j.microrel.2025.115693","DOIUrl":"10.1016/j.microrel.2025.115693","url":null,"abstract":"<div><div>The performance of semiconductor transistors is significantly influenced by charge trapping at oxide and interface defects. The impact of charge-trapping events of defects on the characteristics of the transistor is strongly dependent on factors such as the geometry and the operating point at which the transistor is used. Understanding the complex relationships between the influence of defects and the robustness of devices is essential to optimize circuit performance and becomes particularly important in analog designs. In this work, we investigate the influence of gate oxide defects on the reliability of nanoscale MOS transistors under varying body bias conditions. Using measure-stress-measure techniques, we observe notable effects on both time-zero and time-dependent variability with the application of body bias. Furthermore, the amplitudes of the step heights are investigated as they provide an important measure in scaled technologies to estimate the impact of traps on the device behavior. The results indicate that a body bias can be strategically employed to enhance device reliability by fine-tuning the body bias conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115693"},"PeriodicalIF":1.6,"publicationDate":"2025-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143735211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
扫码关注我们
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号