Enabling of CMOS Circuit using Dual Material Gate Germanium Pocket Induced FDSOI MOSFET

Abstract

This research presents a comparison of the electrical performance of a double-side induced germanium-pocket (IGP) FD-SOI MOSFET and a dual material gate IGPFDSOI (DIGPFDSOI). The electrical performance is reviewed by comparing the device parameters like drain current, band diagram, lateral electric field, surface potential, and work function of the gate material. The proposed structure exhibits excellent characteristics compared to the IGPFDSOI MOSFET. The proposed structure has a greater Ion/Ioff ratio, a lower subthreshold slope, reduced capacitance, and an elevated cut-off frequency. The implementation of a dual metal gate is considered a superior method in comparison to FD-SOI technology because it effectively reduces the negative effects of scaling. A study is being done to analyze the differences in the work functions of metal gates to evaluate the effectiveness of the proposed construction. The comparison evaluation shows that the suggested design can be used for both digital and analog tasks because it has a higher switching frequency and a better cut-off frequency. Apart from this, the proposed structure can also be implemented without making substantial changes to the conventional FD-SOI MOSFET fabrication process flow. Here, we are using n-type and p-type DIGPFDSOI MOSFETs to make a CMOS converter circuit. Sentaurus TCAD is used to simulate and analyze the performance of the proposed structure.