Zhenyun Tang , Zhe Wang , Zhigang Song , Wanhua Zheng
{"title":"Silicon cross-coupled gated tunneling diodes","authors":"Zhenyun Tang , Zhe Wang , Zhigang Song , Wanhua Zheng","doi":"10.1016/j.chip.2024.100094","DOIUrl":null,"url":null,"abstract":"<div><p><strong>Tunneling-based static</strong> <strong>random-access</strong> <strong>memory (SRAM) devices ha</strong><strong>ve</strong> <strong>been developed to fulfill the demands of high density and low power,</strong> <strong>and</strong> <strong>the performance of SRAMs</strong> <strong>has also been greatly promoted</strong><strong>.</strong> <strong>However, for a long time, there has not been a silicon based tunneling device with both high peak valley current ratio (PVCR) and practicality, which remains a gap to be filled</strong><strong>.</strong> <strong>Based on the existing work, the current manuscript proposed the concept of a new silicon-based tunneling device, i.e., the silicon cross-coupled gated tunneling diode (Si XTD), which is quite simple in structure and almost completely compatible with mainstream technology</strong><strong>. With</strong> <strong>t</strong>echnology computer aided design (<strong>TCAD</strong><strong>)</strong> <strong>simulations, it has been validated that this type of device</strong> <strong>not only exhibit</strong><strong>s</strong> <strong>significant</strong> <strong>negative-differential-resistance</strong> <strong>(NDR) behavior with PVCRs up to 10</strong><sup><strong>6</strong></sup><strong>, but also possess</strong><strong>es</strong> <strong>reasonable process margins. Moreover, SPICE simulation</strong> <strong>showed</strong> <strong>the great potential of such devices to achieve</strong> <strong>ultralow-power</strong> <strong>tunneling-based SRAMs with standby power down to 10</strong><sup><strong>−12</strong></sup> <strong>W.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 2","pages":"Article 100094"},"PeriodicalIF":0.0000,"publicationDate":"2024-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472324000121/pdfft?md5=ea45c5d42cfca2586f9abf13cbf43f07&pid=1-s2.0-S2709472324000121-main.pdf","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Chip","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2709472324000121","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Tunneling-based staticrandom-accessmemory (SRAM) devices havebeen developed to fulfill the demands of high density and low power,andthe performance of SRAMshas also been greatly promoted.However, for a long time, there has not been a silicon based tunneling device with both high peak valley current ratio (PVCR) and practicality, which remains a gap to be filled.Based on the existing work, the current manuscript proposed the concept of a new silicon-based tunneling device, i.e., the silicon cross-coupled gated tunneling diode (Si XTD), which is quite simple in structure and almost completely compatible with mainstream technology. Withtechnology computer aided design (TCAD)simulations, it has been validated that this type of devicenot only exhibitssignificantnegative-differential-resistance(NDR) behavior with PVCRs up to 106, but also possessesreasonable process margins. Moreover, SPICE simulationshowedthe great potential of such devices to achieveultralow-powertunneling-based SRAMs with standby power down to 10−12W.