Low latency FPGA implementation of NTT for Kyber

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Microprocessors and Microsystems Pub Date : 2024-04-20 DOI:10.1016/j.micpro.2024.105059

Mohamed Saoudi, Akram Kermiche, Omar Hocine Benhaddad, Nadir Guetmi, Boufeldja Allailou

引用次数: 0

Abstract

This paper presents an FPGA implementation of Number Theoretic Transform (NTT) for the Kyber Post-Quantum Cryptographic (PQC) standard. NTT is the slowest process within Kyber thus a large number of efforts has been conducted to enhance its computational efficiency. Leveraging parallelism and dedicated multipliers, our design achieves state-of-the-art latency, performing NTT/INTT in just 0.4/ $0.5 μ s$ , surpassing existing designs by at least 3.75/3 times. The proposed design is implemented on the cost-effective Artix-7 FPGA.

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Kyber NTT 的低延迟 FPGA 实现

本文介绍了 Kyber 后量子加密（PQC）标准的数论变换（NTT）的 FPGA 实现。NTT 是 Kyber 中速度最慢的处理过程，因此人们为提高其计算效率做了大量工作。利用并行性和专用乘法器，我们的设计实现了最先进的延迟，执行 NTT/INTT 仅需 0.4/0.5μs 的时间，比现有设计至少超出 3.75/3 倍。所提出的设计是在高性价比的 Artix-7 FPGA 上实现的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

Microprocessors and Microsystems 工程技术-工程：电子与电气

CiteScore

6.90

自引率

3.80%

发文量

204

审稿时长

172 days

期刊介绍： Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.

期刊最新文献

Editorial Board Algorithms for scheduling CNNs on multicore MCUs at the neuron and layer levels Low-cost constant time signed digit selection for most significant bit first multiplication An adaptive binary classifier for highly imbalanced datasets on the Edge Quality-driven design of deep neural network hardware accelerators for low power CPS and IoT applications