Ultra-Low Power and Reliable Dynamic Memtransistor Based on Charge Storage Junction FET with Step-Wise Potential Barrier for Energy-Efficient Edge Computing Framework

Abstract

The emergence of technologies such as Artificial Intelligence (AI) and the Internet of Things (IoT) has ushered in the era of big data. The demand for low-power hardware systems and efficient algorithms has become more imperative. In this study, an ultra-low-power dynamic memtransistor based on the charge storage junction Field-Effect Transistor (FET) with a step-wise potential barrier is developed. A simple yet efficient device structure allows for analog programming and spontaneous relaxation. The device demonstrated fast speed (tens of nanoseconds (ns)) and low current (in picoamperes (pA)), resulting in ultra-low programming power (in attojoules (aJ)). Furthermore, the device exhibited high reliability, with a 0.4% cycle-to-cycle variation and endurance over 10⁷ pulses, owing to its non-structural destructive operation process. An operation scheme is developed that enables read on/off and program/inhibition mode for 2T (1 memtransistor-1 selecting transistor) array. The capability to distinguish temporal data using the device's spontaneous relaxation characteristics is demonstrated. A reservoir computing (RC) system framework is constructed using simulation and verified that the dynamic memtransistor can extract features efficiently from a hand-written digit dataset. It is anticipated that the developed dynamic memtransistor, with its distinctive temporal characteristics, will play a pivotal role in developing a novel low-power computing framework.