Mechanism of Threshold Voltage Instability in Double Gate α-IGZO Nanosheet TFT Under Bias and Temperature Stress

IF 2 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of the Electron Devices Society Pub Date : 2024-03-29 DOI:10.1109/JEDS.2024.3406676
Muhammad Aslam;Shu-Wei Chang;Yi-Ho Chen;Yao-Jen Lee;Yiming Li;Wen-Hsi Lee
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Abstract

ABSTRACT Amorphous indium gallium zinc oxide (a-IGZO)-based thin film transistors (TFTs) are increasingly becoming popular because of their potential in futuristic applications, including CMOS technology. Given the demand for CMOS-compatible, ultra-scaled, reliable, and high-performing devices, we fabricate and analyze scaled-channel a-IGZO-TFTs with an optimal double-gate structure, a thin nanosheet-based channel, and an effective high- $\kappa$ dielectric namely HfO2. The reliably reported double gate IGZO nanosheet TFTs (DG-IGZO-NS-TFTs) are tested under positive and negative bias stress at variant temperatures, and the resulting modulations are analyzed critically. The reported DG-IGZO-NSTFTs exhibit a negative side threshold voltage shift ( $\Delta$ Vth) accompanied by an increase in Ion/Ion(0) under negative bias temperature stress (NBTS) at elevated temperatures, which indicates the presence of additional charges. An anomalous negative side shifting of the Vth is observed under positive bias temperature stress (PBTS), where diffused hydrogen atoms are identified as introducing excess n-type carriers into the channel and causing the observed $\Delta$ Vth. The spectroscopic analysis is performed to establish evidence for the assumed mechanisms, and the role of individual gates is investigated in the context of performance variance under temperature-bias stress. Moreover, the partial reversibility of the stress-induced degradation is experimentally established and methodically discussed. Overall, the reported results offer a comprehensive understanding of scaled-channel DG-NS-IGZO-TFTs, which help shape performance-enhancement strategies, control degradation mechanisms, and define appropriate application scenarios.
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偏置和温度应力下双栅α-IGZO 纳米片 TFT 的阈值电压不稳定性机理
摘要 基于非晶铟镓锌氧化物(a-IGZO)的薄膜晶体管(TFT)因其在未来应用(包括 CMOS 技术)中的潜力而越来越受欢迎。鉴于对 CMOS 兼容型、超大规模、可靠和高性能器件的需求,我们制造并分析了具有最佳双栅结构、基于纳米薄片的薄沟道和有效的高 $/kappa$ 介质(即 HfO2)的超大规模沟道 a-IGZO-TFT 。在不同温度下的正负偏压应力条件下测试了可靠报道的双栅极 IGZO 纳米片 TFT(DG-IGZO-NS-TFT),并对由此产生的调制进行了批判性分析。所报告的 DG-IGZO-NSTFT 在高温负偏压温度应力 (NBTS) 下表现出负侧阈值电压偏移($\Delta$ Vth),同时伴随着 Ion/Ion(0) 的增加,这表明存在额外的电荷。在正偏压温度应力(PBTS)下,Vth 出现异常的负侧移,扩散的氢原子被认为是将过量的 n 型载流子引入沟道并导致观察到的 $\Delta$ Vth。光谱分析为假定机制提供了证据,并结合温度偏置应力下的性能差异研究了单个栅极的作用。此外,还通过实验确定并讨论了应力诱导退化的部分可逆性。总之,所报告的结果提供了对缩放沟道 DG-NS-IGZO-TFT 的全面理解,有助于制定性能增强策略、控制退化机制和定义适当的应用场景。
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来源期刊
IEEE Journal of the Electron Devices Society
IEEE Journal of the Electron Devices Society Biochemistry, Genetics and Molecular Biology-Biotechnology
CiteScore
5.20
自引率
4.30%
发文量
124
审稿时长
9 weeks
期刊介绍: The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.
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