Advanced deep-learning-based chip design enabling algorithmic and hardware architecture convergence

Abstract

In order to solve the problems of insufficient computational power and high power consumption of deep learning hardware, the use of deep learning in the field of hardware design is thoroughly investigated, focusing on the design and validation of a hardware gas pedal for Convolutional Neural Networks (CNNs) for target detection. The completeness of the design is ensured by implementing a hardware gas pedal with high computational parallelism using the Verilog HDL language and functional testing using the Universal Verification Methodology UVM. Through module level and system level verification. The experiments confirm the effectiveness of the hardware gas pedal in improving the computational efficiency of the target detection algorithm, contributing valuable insights to the research in the field of deep learning and chip design.