Design of an efficient hybrid cache coherence protocol on chiplet architecture

Abstract

With the continuous development of semiconductor technology, monolithic integration faces problems such as high design costs and long research period. The chiplet effectively improves the yield rate and shortens the research and development cycle by splitting a single die into multiple dies with different functions for advanced packaging integration. However, compared to monolithic integration, inter-die communication is limited by pin density and physical distance, and die interconnects bring higher latency. At the same time, each die has an independent structure, and accessing the same address space will cause system-level cache coherence issues. Therefore, we design a system-level cache based on the directory-based hybrid consistency protocol, and use optimization strategies such as shared bit and add interconnection channels between dies to improve the efficiency of inter-core coherence maintenance. We use GEM5 in conjunction with the SPLASH-2 benchmark to compare with an unoptimized directory-based hybrid coherence protocol. The results show that the program running speed is increased by 19.3%, the average memory access time is reduced by 23.3%, and the consistency protocol traffic is reduced by 37.8%.