Design and power optimization of a QCA-based universal reversible logic gate architecture using cell interaction approach

IF 1.6 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics Reliability Pub Date : 2024-06-20 DOI:10.1016/j.microrel.2024.115446
Aamir Suhail Taray , Satyendra Kumar Singh , Yogesh Singh , Farah Naaz , Purnima Hazra
{"title":"Design and power optimization of a QCA-based universal reversible logic gate architecture using cell interaction approach","authors":"Aamir Suhail Taray ,&nbsp;Satyendra Kumar Singh ,&nbsp;Yogesh Singh ,&nbsp;Farah Naaz ,&nbsp;Purnima Hazra","doi":"10.1016/j.microrel.2024.115446","DOIUrl":null,"url":null,"abstract":"<div><p>This paper introduces a new design for 3 <strong>×</strong> 3 universal and reversible Logic Gate, namely RLG-QCA (reversible logic gate-quantum dot cellular automata) which is implemented using QCA technology. The basic concept of our design is based on the majority voter gate approach (MVA). The suggested gate is designed, simulated and optimized using an accurate QCA cell interaction approach. The proposed gate has no crossover. It has a total area of 0.0311 μm<sup>2</sup> and a latency of 0.5 time period only. To validate its universality, all seven primary logic gates and thirteen Boolean algorithms are realized using the proposed RLG-QCA logic gate. Then a one-bit full adder circuit is constructed with only two numbers of proposed universal logic gates and one coplanar cell crossover. The proposed architecture seems to be an ultra-efficient and stable one with a total cell count of 53 and total cell area of 0.0175 μm<sup>2</sup> and only. Finally, the energy dissipation analysis is also performed on the proposed RLG-QCA gate as well as full adder circuit at different energy levels to confirm the sustainability and suitability of the proposed gate in ultra-low power design applications. The results exhibit extremely low energy dissipation which is an added advantage of the proposed design in implementation of digital circuits with low power dissipation.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115446"},"PeriodicalIF":1.6000,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271424001264","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

Abstract

This paper introduces a new design for 3 × 3 universal and reversible Logic Gate, namely RLG-QCA (reversible logic gate-quantum dot cellular automata) which is implemented using QCA technology. The basic concept of our design is based on the majority voter gate approach (MVA). The suggested gate is designed, simulated and optimized using an accurate QCA cell interaction approach. The proposed gate has no crossover. It has a total area of 0.0311 μm2 and a latency of 0.5 time period only. To validate its universality, all seven primary logic gates and thirteen Boolean algorithms are realized using the proposed RLG-QCA logic gate. Then a one-bit full adder circuit is constructed with only two numbers of proposed universal logic gates and one coplanar cell crossover. The proposed architecture seems to be an ultra-efficient and stable one with a total cell count of 53 and total cell area of 0.0175 μm2 and only. Finally, the energy dissipation analysis is also performed on the proposed RLG-QCA gate as well as full adder circuit at different energy levels to confirm the sustainability and suitability of the proposed gate in ultra-low power design applications. The results exhibit extremely low energy dissipation which is an added advantage of the proposed design in implementation of digital circuits with low power dissipation.

查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
利用单元交互方法设计基于 QCA 的通用可逆逻辑门架构并优化其功耗
本文介绍了一种新的 3 × 3 通用可逆逻辑门设计,即 RLG-QCA(可逆逻辑门-量子点蜂窝自动机),它是利用 QCA 技术实现的。我们设计的基本概念基于多数投票门方法(MVA)。我们采用精确的 QCA 单元交互方法对建议的门进行了设计、模拟和优化。建议的栅极没有交叉。它的总面积为 0.0311 μm2,延迟时间仅为 0.5 个时间周期。为了验证其通用性,我们使用所提出的 RLG-QCA 逻辑门实现了所有七个一级逻辑门和十三种布尔算法。然后,仅用两个拟议的通用逻辑门和一个共面单元分频器就构建了一个一位全加法器电路。所提出的架构似乎是一种超高效且稳定的架构,总单元数为 53 个,总单元面积仅为 0.0175 μm2。最后,还对所提出的 RLG-QCA 栅极以及全加法器电路在不同能级下进行了能量耗散分析,以确认所提出的栅极在超低功耗设计应用中的可持续性和适用性。结果表明,该设计的能耗极低,这也是该设计在实现低功耗数字电路方面的一大优势。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
Microelectronics Reliability
Microelectronics Reliability 工程技术-工程:电子与电气
CiteScore
3.30
自引率
12.50%
发文量
342
审稿时长
68 days
期刊介绍: Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.
期刊最新文献
Editorial Board Comparative study of single event upset susceptibility in the Complementary FET (CFET) and FinFET based 6T-SRAM Effects of humidity, ionic contaminations and temperature on the degradation of silicone-based sealing materials used in microelectronics Physics-of-failure based lifetime modelling for SiC based automotive power modules using rate- and temperature-dependent modelling of sintered silver Study on single-event burnout hardening with reduction of hole current density by top polysilicon diode of SOI LDMOS based on TCAD simulations
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1