Stacked Si Nanosheets Gate-All-Around Transistors with Silicon-on-Nothing Structure for Suppressing Parasitic Effects and Improving Circuits’ Performance

Abstract

We propose a novel silicon-on-nothing (SON) structure with an air sub-fin for suppressing the parasitic channel effects on stacked Si nanosheets (NS) gate-all-around (GAA) transistors and a systematic investigation is carried out by 3D TCAD simulation. The SON structure could be fabricated using a backside selective etching technique. The proposed SON NSFETs with a designed air sub-fin structure demonstrates systematic advantages, including 40% off-state current reduction in the sub-channel, and 51.37% promotion for on-off current ratio (I_ON/I_OFF) and 7.04% reduction in effective capacitance. Moreover, there is approximately 21.62% power reduction under the same frequency, and about 16.30% energy reduction under the same delay in 17-stage ring oscillators (ROs). The SON NSFETs-based 6T-SRAM exhibits decreased read time and write time by 14.66% and 67.53%, respectively, compared with those of the conventional GAA NSFETs-based 6T-SRAM.