Characterizing parameter variations for enhanced performance and adaptability in 3 nm MBCFET technology

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics Journal Pub Date : 2024-07-14 DOI:10.1016/j.mejo.2024.106338
Mahmood Rafiee , Nabiollah Shiri , Mohsen Gharehkhani , Alexandra Pinto Castellanos , Ayoub Sadeghi
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Abstract

With the continuous scaling down of semiconductor devices, traditional transistor architectures face significant challenges in maintaining performance and power efficiency. Multi-bridge channel field-effect transistors (MBCFETs) are promising candidates for next-generation of transistors, enabling significant size reduction while preserving high performance. This paper investigates both n-type and p-type 3-nm MBCFETs with a focus on their behavior under diverse operating conditions. The study examines the influence of doping concentration, sheet thickness, temperature, device width, and the number of sheets, on the device's functionality aiming for high-performance applications. Doping concentrations of acceptors and donors ranging from 1 × 10 15 cm−3 - 9 × 10 17 cm−3 and 1 × 10 17 cm−3 - 9 × 10 19 cm−3, respectively, to observe their impact on device performance. Similarly, sheet thicknesses from 1 nm to 2 nm and device widths from 3 nm to 30 nm are analyzed to understand the scaling effects. The temperature varies from 273.15 K to 573.15 K to simulate different operational environments, while the number of sheets, ranging from 1 to 7, is adjusted to evaluate structural effects on device behavior. By extracting the subthreshold swing (SS), threshold voltage (Vth), ON-current (ION), OFF-current (IOFF), and the ION/IOFF ratio, the study offers valuable insights into the suitability and potential applications of N-MBCFET and P-MBCFET devices at the ultra-scaled 3 nm dimension. At room temperatures, the SS achieves 60 mV dec⁻1 for n-type and 64 mV dec⁻1 for p-type which indicates proper switching speed, with corresponding ON/OFF ratios of 2 × 106 and 1 × 105 for n-type and p-type, respectively. This study makes notable contributions to the field of nanoscale transistor technology, aiding in the design and optimization of future electronic devices.

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表征参数变化,提高 3 纳米 MBCFET 技术的性能和适应性
随着半导体器件规模的不断缩小,传统晶体管架构在保持性能和能效方面面临着巨大挑战。多桥沟道场效应晶体管(MBCFET)是下一代晶体管的理想候选器件,可在保持高性能的同时显著缩小尺寸。本文研究了 n 型和 p 型 3 纳米 MBCFET,重点关注它们在不同工作条件下的行为。研究探讨了掺杂浓度、薄片厚度、温度、器件宽度和薄片数量对器件功能的影响,旨在实现高性能应用。受体和供体的掺杂浓度范围分别为 1 × 10 15 cm-3 - 9 × 10 17 cm-3 和 1 × 10 17 cm-3 - 9 × 10 19 cm-3,以观察它们对器件性能的影响。同样,还分析了 1 nm 至 2 nm 的薄片厚度和 3 nm 至 30 nm 的器件宽度,以了解缩放效应。温度从 273.15 K 到 573.15 K 不等,以模拟不同的工作环境,而薄片数量则从 1 到 7 不等,以评估结构对器件行为的影响。通过提取阈下摆幅 (SS)、阈值电压 (Vth)、导通电流 (ION)、关断电流 (IOFF) 以及 ION/IOFF 比值,该研究为 3 纳米超大规模 N-MBCFET 和 P-MBCFET 器件的适用性和潜在应用提供了宝贵的见解。在室温条件下,N 型和 P 型的 SS 分别达到了 60 mV dec-1 和 64 mV dec-1,这表明开关速度合适,相应的导通/关断比分别为 2 × 106 和 1 × 105。这项研究为纳米级晶体管技术领域做出了突出贡献,有助于未来电子器件的设计和优化。
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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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