Microelectronics Journal最新文献

A stacked regression–based TCAD–ML framework for accelerated GaN transistor design 基于堆叠回归的加速GaN晶体管设计TCAD-ML框架

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2026-01-31 DOI: 10.1016/j.mejo.2026.107086

Menglan Ji , Tianhao Wang , Yuanfeng Chen , Yuqi Zhang , Guanjun Wang , Jialin Zhang

Traditional Technology Computer-Aided Design (TCAD) simulations face significant challenges in meeting the demands of high-throughput device design, particularly for wide-bandgap semiconductor devices such as GaN transistors, where numerical convergence issues and high computational costs are prevalent. To address these limitations, this work proposes a stacked regression–based TCAD–machine learning (TCAD-ML) framework for efficient and accurate prediction of the electrical characteristics of GaN heterojunction field-effect transistors (HFETs). The framework integrates a fully connected neural network and an XGBoost model as base learners, with a Random Forest meta-learner to exploit complementary latent features. Using only 480 training samples generated from calibrated TCAD simulations, the proposed model achieves high prediction accuracy for both transfer and output characteristics, with R² values exceeding 0.999. Furthermore, a successive approximation strategy is introduced to mitigate the impact of TCAD non-convergence in certain design regions, enabling reliable prediction in parameter spaces inaccessible to conventional simulations. Compared with existing machine learning–based device models, the proposed approach demonstrates superior accuracy, strong few-shot learning capability, and excellent generalization performance. These results highlight the potential of stacked regression–based TCAD-ML frameworks as an effective alternative to traditional TCAD for accelerating GaN transistor design and optimization.

传统的计算机辅助设计（TCAD）模拟技术在满足高通量器件设计需求方面面临重大挑战，特别是对于宽带隙半导体器件，如GaN晶体管，其中数值收敛问题和高计算成本普遍存在。为了解决这些限制，本研究提出了一种基于堆叠回归的tcad -机器学习（TCAD-ML）框架，用于高效准确地预测GaN异质结场效应晶体管（hfet）的电特性。该框架集成了一个完全连接的神经网络和一个XGBoost模型作为基础学习器，以及一个随机森林元学习器来利用互补的潜在特征。仅使用校准后的TCAD模拟生成的480个训练样本，该模型对传递特性和输出特性的预测精度都很高，R2值超过0.999。此外，引入了一种逐次逼近策略来减轻TCAD在某些设计区域不收敛的影响，从而在常规模拟无法获得的参数空间中实现可靠的预测。与现有的基于机器学习的设备模型相比，该方法具有较高的准确率、较强的小样本学习能力和良好的泛化性能。这些结果突出了基于堆叠回归的TCAD- ml框架作为加速GaN晶体管设计和优化的传统TCAD的有效替代方案的潜力。

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引用次数: 0

Design of a compact and low-loss bulk acoustic wave filter for the BeiDou B1C band 北斗B1C波段小型低损耗体声波滤波器设计

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2026-01-27 DOI: 10.1016/j.mejo.2026.107076

Jie Tang , Weipeng Xuan , Rui Ding , Yiran Wei , Feng Gao , Jikui Luo , Shurong Dong

This paper presents a compact, low-loss narrowband bulk acoustic wave (BAW) ladder filter for the BeiDou-3 B1C band. An enhanced Mason equivalent-circuit model is employed, enabling concurrent optimization of resonator characteristics and filter response. To meet the stringent 32.736 MHz bandwidth, the effective electromechanical coupling coefficient (k_eff²) is intentionally reduced through engineering of the electrode-to-piezoelectric thickness ratio (t_e/t_p ≈ 2.3–2.5). A ladder topology with individually tailored resonator areas is co-optimized to balance insertion loss, out-of-band rejection, chip area, and power handling. The fabricated AlN BAW resonator exhibits an effective k_eff² of 3.9 %, a maximum quality factor (Q_max) of 3346 at 1.578 GHz, and a temperature coefficient of frequency (TCF) of approximately −31.75 ppm/°C. The resulting filter achieves a minimum in-band insertion loss of 1.16 dB, out-of-band suppression exceeding 36.6 dB, and an effective filter-level TCF of −30.5 ppm/°C. With a compact area of 0.82 × 0.62 mm², the filter demonstrates a miniaturized, high-performance solution for BeiDou-3 B1C application.

提出了一种适用于北斗三号B1C波段的紧凑、低损耗窄带体声波（BAW）梯形滤波器。采用增强型梅森等效电路模型，可同时优化谐振器特性和滤波器响应。为了满足严格的32.736 MHz带宽，通过设计电极-压电厚度比（te/tp≈2.3-2.5），有意降低有效机电耦合系数（keff2）。具有单独定制谐振器区域的梯形拓扑进行了协同优化，以平衡插入损耗、带外抑制、芯片面积和功率处理。所制备的AlN BAW谐振器在1.578 GHz时的有效keff2为3.9%，最大质量因子（Qmax）为3346，频率温度系数（TCF）约为- 31.75 ppm/°C。该滤波器的带内插入损耗最小为1.16 dB，带外抑制超过36.6 dB，有效滤波器电平TCF为- 30.5 ppm/°C。该滤波器面积为0.82 × 0.62 mm2，为北斗3号B1C应用提供了小型化、高性能的解决方案。

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引用次数: 0

A semi-injection CML frequency divider and application for high speed prescaler 半注入式CML分频器及其在高速预分频器中的应用

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2026-01-24 DOI: 10.1016/j.mejo.2026.107068

Leilei Xiao, Xiuping Li, Yubing Li, Chen Yan, Xu Ji

To address the challenge of high input capacitance in conventional current mode logic (CML) frequency dividers for high-frequency on-chip systems, this paper presents a novel Semi-Injection CML (SI-CML) frequency divider. In contrast to conventional CML frequency dividers, where the input differential signal simultaneously drives the clock transistors of both coupling (C) and negative-

g_{m}

(N) cells, the proposed SI-CML frequency divider is designed to drive only the clock transistors of the C cell. This approach achieves a lower input parasitic capacitance — a key advantage for high-frequency scenarios — while maintaining excellent performance. As proof, a prescaler containing SI-CML frequency divider is designed using a 110 nm CMOS technology. By estimating the power consumption of the prescaler, it is demonstrated that the introduction of Semi-Injection (SI) mode improves power consumption. Compared with differential injection (DI) mode, the first stage SI-CML frequency divider reduces the input capacitance from 51fF to 37fF, while achieving a wide lock-in range of 7-35 GHz (160%) and a Figure-of-Merit (FoM) of 22.9 dB. Finally, the prescaler was successfully integrated into the K-band radar chip.

为解决高频片上系统中传统电流模逻辑分频器输入电容高的问题，提出了一种新型半注入式电流模逻辑分频器。在传统的CML分频器中，输入差分信号同时驱动耦合(C)和负gm (N)单元的时钟晶体管，与之相反，所提出的SI-CML分频器被设计为仅驱动C单元的时钟晶体管。这种方法实现了较低的输入寄生电容-高频场景的关键优势-同时保持优异的性能。作为证明，采用110纳米CMOS技术设计了包含SI-CML分频器的预分频器。通过对预衡器功耗的估算，证明了半注入（SI）模式的引入改善了功耗。与差分注入（DI）模式相比，第一级SI-CML分频器将输入电容从51fF降低到37fF，同时实现了7-35 GHz（160%）的宽锁相范围和22.9 dB的性能因数（FoM）。最后，将预分频器成功集成到k波段雷达芯片中。

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引用次数: 0

A novel P/N-drift reverse-conducting IGBT with P-layer structure at the trench bottom 一种新型的P/ n漂移反导IGBT，在海沟底部具有P层结构

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2026-01-21 DOI: 10.1016/j.mejo.2026.107072

Zhigang Shen, Wensuo Chen

In this study, a novel reverse-conducting (RC) insulated gate bipolar transistor (IGBT) is proposed and investigated. This device possesses two core structural features: first, it adopts P/N-drift region; second, it has P-layer (PL) structure positioned at the trench bottom. Based on these features, the device is named PNPL-IGBT. The PL structure address the reverse turn-on delay issue in conventional P-drift RC-IGBT (PD-IGBT), which is caused by the difficulty of the P-drift region to rapidly recover from the depleted state before the reverse turn-on. Meanwhile, the PL structure can effectively suppress the negative gate capacitance effect that occurs in PD-IGBT. However, the P-drift RC-IGBT with PL structure at the trench bottom (PDPL-IGBT) exhibits high maximum reverse recovery dV_EC/dt (dV_EC/dt_rr,max). Compared with the P-drift region, the P/N-drift region delays the establishment of the electric field in the drift region during the reverse recovery, thereby reducing the dV_EC/dt_rr,max. Simulation results show that, compared with the NDPL-IGBT, the proposed PNPL-IGBT achieves 40.07 % reduction in forward turn-off loss (E_off) at the same forward conduction voltage (V_F) of 1.21 V. Furthermore, the dV_EC/dt_rr,max of the PNPL-IGBT is reduced by 39.28 % compared to the PDPL-IGBT.

本文提出并研究了一种新型的反导（RC）绝缘栅双极晶体管（IGBT）。该器件具有两个核心结构特点：一是采用P/ n漂移区；二是在海沟底部有p层（PL）结构。基于这些特点，该设备被命名为PNPL-IGBT。PL结构解决了传统p漂RC-IGBT （PD-IGBT）中由于p漂区难以从反向导通前的耗尽状态快速恢复而导致的反向导通延迟问题。同时，PL结构可以有效抑制PD-IGBT中出现的负栅电容效应。而在海沟底部具有PL结构的p漂移RC-IGBT （PDPL-IGBT）具有较高的最大反向恢复dVEC/dt （dVEC/dtrr,max）。与P漂移区相比，P/ n漂移区延迟了反向恢复过程中漂移区电场的建立，从而降低了dVEC/dtrr。仿真结果表明，在相同的正向导通电压（VF）为1.21 V时，与NDPL-IGBT相比，PNPL-IGBT的正向关断损耗（Eoff）降低了40.07%。此外，PNPL-IGBT的dVEC/dtrr，max比PDPL-IGBT降低了39.28%。

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引用次数: 0

A low-power self-reference Class-C VCO with dual feedback loops 具有双反馈回路的低功耗自参考c类压控振荡器

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2026-01-21 DOI: 10.1016/j.mejo.2026.107069

Zushuai Xie , Haojie Gong , Bo Gu , Chenggang Yan , Jingjing Guo , Lu Liu , Guoqing Li , Tinghuan Chen , Zhikuang Cai , Zixuan Wang

This paper presents a low-power, self-referenced class-C voltage-controlled oscillator (VCO) with dual feedback loops. To reduce the system complexity and power consumption of class-C VCOs, a self-referenced dual-feedback-loop topology is proposed. The first loop is a negative-amplitude-detection loop, which generates a reference voltage V_ref without requiring an external circuit, thereby avoiding additional power consumption. The second loop is a common-source-node feedback loop, which adaptively adjusts the bias voltage of the cross-coupled pair to achieve dynamic biasing and ensure oscillation startup. The proposed VCO is implemented in a 22-nm CMOS process, consuming only 0.49 mW under a 0.6-V supply voltage, with a frequency tuning range is 36.4 % from 3.6 to 5.2 GHz. Experimental results exhibit phase noise (PN) of −110 dBc/Hz at a 1-MHz offset and a figure of merit (FoM) of −186 dBc/Hz at a 4.4-GHz carrier frequency.

提出了一种低功耗、自参考的双反馈回路c类压控振荡器（VCO）。为了降低c类压控振荡器的系统复杂度和功耗，提出了一种自参考双反馈环拓扑结构。第一个环路是负幅度检测环路，它产生参考电压Vref而不需要外部电路，从而避免了额外的功耗。第二环为共源节点反馈环，自适应调节交叉耦合对的偏置电压，实现动态偏置，保证振荡启动。该VCO采用22nm CMOS工艺实现，在0.6 v电源电压下功耗仅为0.49 mW，频率调谐范围为36.4%，从3.6 GHz到5.2 GHz。实验结果表明，在1 mhz偏置时，相位噪声（PN）为−110 dBc/Hz，在4.4 ghz载波频率下，性能因数（FoM）为−186 dBc/Hz。

引用次数: 0

Mechanism and pattern of Micro-Cu pillar array interconnection in electroplating bonding using a single-accelerator system 单加速器系统电镀键合中微铜柱阵列互连的机理和模式

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2026-01-21 DOI: 10.1016/j.mejo.2026.107073

Yuting Zhong , Haoze Yang , Qiang Zhang , Junhui Li

Electroplating bonding technology enables high-density, room-temperature, and pressure-free Cu-Cu interconnection, making it a key focus in advanced packaging. This study investigates two accelerators, sodium polystyrene sulfonate (SPS) and thiazolidine dithiopropane sulfonic acid sodium salt (SH110). A micro-Cu pillar array bonding process is proposed, and finite element simulation reveals the “conformal deposition” characteristic in single-accelerator systems. Experiments show that single-accelerator systems yield thicker deposits with limited bonding quality. Single bumps exhibit conformal deposition, and single-row plating presents a “thick-at-entrance and thin-in-middle” feature. After convection enhancement (from 100 μL/min to 200 μL/min), the SPS system shows a 30.5 % increase in non-uniformity of plating thickness, and the interconnection success rate rises from 31.3 % to 100 %. In contrast, the SH110 system shows a 56.7 % decrease in non-uniformity and a drop in success rate from 50 % to 31.3 %. These results provide new insights for optimizing Cu–Cu electroplating bonding processes.

电镀键合技术可实现高密度、室温、无压力的Cu-Cu互连，使其成为先进封装的关键焦点。研究了聚苯乙烯磺酸钠（SPS）和噻唑烷二硫丙烷磺酸钠盐（SH110）两种促进剂。提出了一种微铜柱阵列键合工艺，并通过有限元模拟揭示了单加速器系统的“保形沉积”特性。实验表明，单加速体系的镀层较厚，但结合质量有限。单个凸起呈现保形沉积，单排镀层呈现“入口厚，中间薄”的特征。对流增强后（从100 μL/min提高到200 μL/min）， SPS系统的镀层厚度不均匀性提高30.5%，互连成功率从31.3%提高到100%。相比之下，SH110系统的不均匀性降低了56.7%，成功率从50%下降到31.3%。这些结果为优化Cu-Cu电镀键合工艺提供了新的思路。

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引用次数: 0

A compact bias-dependent body resistance model for partially depleted silicon-on-insulator MOSFETs 部分耗尽绝缘体上硅mosfet的紧凑偏置体电阻模型

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2026-01-20 DOI: 10.1016/j.mejo.2026.107059

Tianye Yu , Gongteng Xiao , Yudi Zhao , Shiyou Chen , Guangxi Hu , Ye Lu

In this work, a compact, bias-dependent non-linear body resistance model is developed and verified for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs. The model includes two parts: one is the resistance related to the majority carriers that move along the width direction, and the other is the body-source p-n junction resistance. For the former part, the calculation is based on the charge of majority carriers in the neutral body region, which includes the calculations of the front/back gates depletion (accumulation) charges and the source/drain depletion charges. For the latter part, it can be determined with the use of the body-source p-n junction conductance. The model is verified against experiments and TCAD simulations, both with good agreements. The model is tested quantitatively, the worst case average relative error is 4.4 %. Furthermore, the model can capture the body resistances of the PD SOI MOSFETs of different geometries accurately. Only five fitting parameters are included, and the computation is efficient.

在这项工作中，开发并验证了部分耗尽（PD）绝缘体上硅（SOI） mosfet的紧凑，偏置相关的非线性体电阻模型。该模型包括两部分：一部分是与沿宽度方向移动的大多数载流子相关的电阻，另一部分是体源p-n结电阻。对于前者，计算基于中性体区域大多数载流子的电荷，其中包括前/后门耗尽（积累）电荷和源/漏耗尽电荷的计算。对于后一部分，可以使用体源p-n结电导来确定。通过实验和TCAD仿真验证了模型的正确性。对模型进行了定量测试，最坏情况下的平均相对误差为4.4%。此外，该模型可以准确捕获不同几何形状的PD SOI mosfet的体电阻。该方法只包含5个拟合参数，计算效率高。

引用次数: 0

A fractional-N frequency synthesizer incorporating phase synchronization and frequency-modulated continuous-wave (FMCW) capabilities 结合相位同步和调频连续波（FMCW）功能的分数n频率合成器

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2026-01-20 DOI: 10.1016/j.mejo.2026.107070

Kaiwen Zheng , Changchun Zhang , Yi Zhang , Jing Wang

A fractional-N frequency synthesizer (FS) incorporating phase synchronization and frequency-modulated continuous-wave technique is proposed in 65 nm CMOS technology. Direct phase detection is achieved by utilizing the output reference signals of a numerically controlled oscillator (NCO) and the FS output clock signals that have been under-sampled by the reference clock to perform trigonometric function operation concurrently. By providing the first-order accumulator of the third-order delta-sigma modulator (DSM) with continuous phase adjustment values, the issue of multi-chip output clock inconsistency, arising from DSM output sequence shifts and non-ideal factors, is effectively solved. Based on the FS core, a programmable chirp slope is also proposed to make the FS output FMCW, and an additional current is injected to increase the down-chirp slope during the sawtooth wave down-chirp segment. The simulation results show that the FS achieves an overall frequency range of 0.4–11.0 GHz, a phase synchronization time of less than 20.2 μs, a phase error of 0.4° post-synchronization, a chirp frequency range of 9.605–10.885 GHz, and a power consumption of 114.3 mW at a 1.2 V supply voltage.

提出了一种结合相位同步和调频连续波技术的分数n频率合成器（FS）。直接相位检测是通过利用数控振荡器（NCO）的输出参考信号和经参考时钟欠采样的FS输出时钟信号并行执行三角函数运算来实现的。通过为三阶delta-sigma调制器（DSM）的一阶蓄能器提供连续相位调整值，有效解决了由于DSM输出序列移位和非理想因素引起的多芯片输出时钟不一致问题。在此基础上，提出了一个可编程的啁啾斜率，使FS输出FMCW，并在锯齿波下啁啾段注入额外的电流以增加下啁啾斜率。仿真结果表明，在1.2 V电源电压下，该系统的总频率范围为0.4 ~ 11.0 GHz，相位同步时间小于20.2 μs，同步后相位误差为0.4°，啁啾频率范围为9.605 ~ 10.885 GHz，功耗为114.3 mW。

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引用次数: 0

A monolithic integrated quantum random number generation based on Band-to-Band tunneling effect 基于带间隧道效应的单片集成量子随机数生成

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2026-01-19 DOI: 10.1016/j.mejo.2026.107071

Feiqiang Li , Dunwei Liu , Wenshu Chen , Siyu He , Yujie Huang , Xin Lv , Zhiyuan Tan , Mingyu Wang , Xiaoyang Zeng

This paper presents a monolithically integrated quantum random number generator (QRNG) that utilizes the band-to-band tunneling (BTBT) effect in a single-photon avalanche diode (SPAD) as a robust entropy source. To achieve high-quality randomness, we designed a dedicated SPAD structure through TCAD simulations, optimizing it for a dominant BTBT component. The simulation results demonstrate that the proposed structure offers a high tunneling event rate while maintaining a high proportion of BTBT-induced counts. The generated random numbers are derived from the time intervals between successive tunneling events, followed by post-processing using an AES encryption module and throughput enhancement via a linear-feedback shift register (LFSR). The QRNG was finally fabricated in a 180 nm CMOS process. Experimental measurements show a raw tunneling pulse rate of 67 kcps and a random numbers rate of 25 Mbit/s after digital post-processing. The output successfully passes both the NIST SP800-22 and the Chinese national standard GM/T0005-2021 randomness test, confirming its quality and suitability for secure applications.

本文提出了一种单片集成量子随机数发生器（QRNG），该发生器利用单光子雪崩二极管（SPAD）中的带对带隧道效应作为鲁棒熵源。为了获得高质量的随机性，我们通过TCAD仿真设计了一个专用的SPAD结构，并对其进行了优化。仿真结果表明，该结构提供了高隧道事件率，同时保持了高比例的btbt诱导计数。生成的随机数来源于连续隧道事件之间的时间间隔，随后使用AES加密模块进行后处理，并通过线性反馈移位寄存器（LFSR）增强吞吐量。最后在180 nm的CMOS工艺中制备了QRNG。实验测量表明，经过数字后处理的原始隧道脉冲速率为67 kcps，随机数速率为25 Mbit/s。输出产品通过NIST SP800-22和中国国家标准GM/T0005-2021随机测试，验证了其质量和安全应用的适用性。

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引用次数: 0

Design and implementation of full adder using negative differential resistance circuits based on CMOS process 基于CMOS工艺的负差分电阻全加法器的设计与实现

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2026-01-17 DOI: 10.1016/j.mejo.2026.107064

Kwang-Jow Gan, Li-Cheng Zhang

This paper presents the design and implementation of a 1-bit full adder using MOS-based negative differential resistance (MOS-NDR) circuits fabricated in a standard 0.18 μm CMOS process. The proposed design is based on the monostable–bistable transition logic element (MOBILE) principle, where bistable switching is determined by the relative peak currents of the load and driver NDR stages. The fabricated circuit demonstrates clear MOBILE-like switching behavior, verifying the feasibility of implementing NDR-based digital logic entirely within a CMOS-compatible process. The measured I–V characteristics exhibit a Λ-shaped NDR curve consistent with simulation results, and the full adder achieves correct sum and carry operations. Furthermore, the peak current I_P of the MOS-NDR circuit can be tuned between 1 mA and 3 mA by adjusting the bias voltage V_GG, allowing post-fabrication adjustment of logic characteristics. The results demonstrate that MOS-NDR circuits offer an effective alternative for constructing energy-efficient and compact arithmetic logic units without requiring non-silicon materials.

本文介绍了一种基于mos的负差分电阻（MOS-NDR）电路的1位全加法器的设计和实现，该电路采用标准0.18 μm CMOS工艺制造。提出的设计基于单稳-双稳转换逻辑元件（MOBILE）原理，其中双稳切换由负载和驱动器NDR级的相对峰值电流决定。制造的电路显示了清晰的类似于mobile的开关行为，验证了在cmos兼容过程中完全实现基于ndr的数字逻辑的可行性。实测的I-V特性呈现与仿真结果一致的Λ-shaped NDR曲线，全加法器实现了正确的和和进位运算。此外，通过调整偏置电压VGG， MOS-NDR电路的峰值电流IP可以在1 mA和3 mA之间进行调谐，从而可以在制作后调整逻辑特性。结果表明，MOS-NDR电路为构建节能和紧凑的算术逻辑单元提供了有效的替代方案，而不需要非硅材料。

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引用次数: 0