Microelectronics Journal最新文献

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Frequency and time-domain analysis of shield differential multibit TGV using EM-RA technique for 3D integrated circuits 三维集成电路屏蔽差分多比特TGV频域和时域分析

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2025-12-11 DOI: 10.1016/j.mejo.2025.107014

Ajay Kumar , Amit Kumar , Ashish Singh

This paper presents a comprehensive electrical modeling framework for shield differential multibit - through glass via (DM-TGV) structure envisioned for three-dimensional (3D) integrated circuits. Closed-form mathematical expressions for the via resistance, inductance, capacitance, and conductance are formulated directly from its geometric attributes. The effective complex conductivity of carbon nanotube (CNT) is extracted with frequency at various diameter of CNT. The exponential matrix - rational approximation (EM-RA) technique is employed to investigate its high-frequency performance, enabling the extraction of frequency-dependent parameters such as the magnitude of S₂₁ under differential and common-mode excitation for different filler materials and via heights across a wide spectral range. The analytical results are corroborated through full-wave simulations using the high frequency structure simulator (HFSS). Transient-domain behavior of the shield DM-TGV is further examined by incorporating variations in temperature, and surface roughness with their values spanning 300–500K and 150–1500 nm, respectively. Transfer characteristics are evaluated for multiple filler configurations and via dimensions, and the results obtained are compared with both conventional multibit differential TGVs and coaxial through-silicon vias (C-TSVs). It has been observed that the proposed shield DM-TGV provides substantially improved bandwidth relative to C-TSVs. In addition, Nyquist stability validation using EM-RA is carried out for different material fillings and via heights. The shield DM-TGV demonstrates superior stability when benchmarked against C-TSVs and conventional DM-TGVs, establishing it as a more reliable alternative for high-frequency 3D on-chip interconnects.

本文提出了一种用于三维集成电路的屏蔽差分多位通玻璃孔（DM-TGV）结构的综合电气建模框架。通过电阻，电感，电容和电导的封闭形式的数学表达式是直接从其几何属性制定的。利用频率提取了碳纳米管在不同直径下的有效复合电导率。采用指数矩阵有理近似（EM-RA）技术研究其高频性能，能够提取频率相关参数，例如不同填充材料在差分和共模激励下的S21的大小，以及在宽光谱范围内的高度。利用高频结构模拟器（HFSS）进行全波仿真，验证了分析结果。通过结合温度和表面粗糙度的变化（分别为300-500K和150-1500 nm），进一步研究了屏蔽DM-TGV的瞬态域行为。评估了多个填料配置和通孔尺寸的传输特性，并将所得结果与传统的多位差分tgv和同轴硅通孔（c - tsv）进行了比较。已经观察到，相对于c - tsv，所提出的屏蔽DM-TGV提供了显著改善的带宽。此外，使用EM-RA对不同的材料填充和通孔高度进行了Nyquist稳定性验证。当与c - tsv和传统DM-TGV进行基准测试时，屏蔽DM-TGV表现出卓越的稳定性，使其成为高频3D片上互连的更可靠替代方案。

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引用次数: 0

A 14-bit 3 GS/s pipelined ADC featuring an input buffer with replica-based nonlinearity compensation in 28-nm CMOS technology 采用28纳米CMOS技术的14位3 GS/s流水线ADC，具有基于复制的非线性补偿输入缓冲器

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2025-12-10 DOI: 10.1016/j.mejo.2025.107015

Nannan Li , Lei Pei , Bin Liu , Hanrui Zhang , Jinfu Wang , Jie Zhang , Xiaofei Wang , Hong Zhang

This paper presents a 3-GS/s 14-bit pipelined analog-to-digital converter (ADC) comprising an ADC core circuit, an on-chip reference circuitry, and a JESD204B serial interface for high-speed communication systems. The ADC core adopts a sample-and-hold amplifier-less (SHA-less) structure with five 3-bit pipelined stages followed by a final 4-bit flash ADC stage. In order to realize an easy-drive ADC front end with low power consumption, a source-follower-based (SFB) input buffer is integrated on chip to isolate the ADC's switch-capacitor (SC) sampling network and the external signal source. To suppress the heavy nonlinearity in the SFB input buffer, a replica-based compensation structure is proposed in which the nonlinear current flowing through the sampling capacitance is replicated to the common-mode (CM) voltage buffer for sampling via a current mirror. By simultaneously sampling both the input signal and the modulated CM voltage through the sampling capacitor, the nonlinearity is canceled significantly. The ADC with the nonlinearity-compensated input buffer is fabricated in a 28-nm CMOS process, occupying an active area of 1.46 mm². With a 2.5 V supply for the input buffer and 1 V supply for the ADC core, measurement results show that the full ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 61.08 dB and a spurious-free dynamic range (SFDR) of 75.93 dB, consuming 1.4 W of total power.

本文提出了一种用于高速通信系统的3-GS/s 14位流水线模数转换器（ADC），它由ADC核心电路、片上参考电路和JESD204B串行接口组成。ADC核心采用无采样保持放大器（SHA-less）结构，具有5个3位流水线级，最后是4位闪存ADC级。为了实现低功耗、易于驱动的ADC前端，在芯片上集成了一个基于源跟踪器（SFB）的输入缓冲器，以隔离ADC的开关电容（SC）采样网络和外部信号源。为了抑制SFB输入缓冲器中的严重非线性，提出了一种基于复制的补偿结构，通过电流镜将流经采样电容的非线性电流复制到共模电压缓冲器中进行采样。通过采样电容同时对输入信号和调制后的CM电压进行采样，显著地消除了非线性。具有非线性补偿输入缓冲器的ADC采用28纳米CMOS工艺制造，占据1.46 mm2的有效面积。在2.5 V输入缓冲器和1 V ADC核心供电的情况下，测量结果表明，整个ADC的信噪比（SNDR）为61.08 dB，无杂散动态范围（SFDR）为75.93 dB，总功耗为1.4 W。

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引用次数: 0

Dual barrier with recessed gate GaN HEMTs for improved DC and RF performance 双势垒与嵌入式栅极GaN hemt，改善直流和射频性能

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2025-12-09 DOI: 10.1016/j.mejo.2025.107013

Zilong Huang, Yuan Li, Xinman Chen, Daibo Yin, Zhiyou Guo, Huiqing Sun

A study was conducted on enhancement-mode GaN HEMTs with a novel dual barrier recess gate structure, and their DC and RF characteristics were simulated using the SILVACO TCAD tool. In the new structure, the barrier layer is divided into two layers: the first layer adopts a fixed Al composition concentration, while the second layer uses a graded Al composition concentration. The results demonstrate that, compared with the conventional device, the proposed structure achieves a threshold voltage of 0.9 V, an increase in maximum saturation drain current from 0.84 A/mm to 1.12 A/mm, and a rise in peak transconductance from 0.29 S/mm to 0.44 S/mm. In terms of RF performance, the current gain cutoff frequency and the unilateral power gain cutoff frequency of the new structure are improved from 12.98 GHz to 23.22 GHz and from 23.75 GHz to 47.91 GHz, respectively. Finally, the corresponding variations in electrical properties are systematically analyzed, providing physical insights into the underlying mechanisms.

研究了具有新型双势垒凹槽栅极结构的增强模式GaN hemt，并利用SILVACO TCAD工具对其直流和射频特性进行了仿真。在新结构中，阻隔层分为两层：第一层采用固定的Al成分浓度，而第二层采用渐变的Al成分浓度。结果表明，与传统器件相比，该结构实现了0.9 V的阈值电压，最大饱和漏极电流从0.84 a /mm增加到1.12 a /mm，峰值跨导从0.29 S/mm增加到0.44 S/mm。在射频性能方面，新结构的电流增益截止频率和单侧功率增益截止频率分别从12.98 GHz提高到23.22 GHz和23.75 GHz提高到47.91 GHz。最后，系统地分析了相应的电性能变化，为潜在机制提供了物理见解。

引用次数: 0

A neural network-optimized broadband RF rectifier with wide dynamic range 一种神经网络优化的宽动态范围宽带射频整流器

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2025-12-08 DOI: 10.1016/j.mejo.2025.107011

Jialu Wang, Fabin Fan, Xiaofang Wu

To achieve both wide bandwidth and wide dynamic range, a rectifier with adaptive power allocation method is designed, and a broadband matching network using neural network optimization is proposed. The rectifier consists of two broadband rectifier branches operating in different input power ranges and utilizes the different input impedances of the branches at different input power levels to achieve automatic power allocation. The optimization of the matching network for each branch using neural networks reduces the computational cost and simplifies the design process. The proposed rectifier is validated by simulation analysis and practical tests. Measurements show that the rectifier is more than 50% efficient over the frequency range of 0.31 to 1.38 GHz, with a peak efficiency of 82% at 25 dBm input power. At 0.6 GHz, the rectifier is more than 50% efficient over the input power range of 7.5 to 33.5 dBm, with a dynamic range of 26 dB.

为了同时实现宽带宽和宽动态范围，设计了一种自适应功率分配方法的整流器，并提出了一种基于神经网络优化的宽带匹配网络。该整流器由两个工作在不同输入功率范围的宽带整流支路组成，利用不同输入功率水平支路的不同输入阻抗实现功率自动分配。利用神经网络对各分支的匹配网络进行优化，降低了计算成本，简化了设计过程。仿真分析和实际测试验证了该整流器的有效性。测量表明，整流器在0.31至1.38 GHz的频率范围内效率超过50%，在25 dBm输入功率下的峰值效率为82%。在0.6 GHz时，整流器在7.5至33.5 dBm的输入功率范围内效率超过50%，动态范围为26 dB。

引用次数: 0

A RISC-V based heterogeneous neuromorphic system with dynamic reconfigurable computing for edge AI 基于RISC-V的边缘人工智能异构神经形态系统动态可重构计算

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2025-12-04 DOI: 10.1016/j.mejo.2025.107007

Zhaotong Zhang , Yi Zhong , Zilin Wang , Youming Yang , Tao Zhang , Jinhao Ruan , Yipeng Gao , Yuan Wang

Neuromorphic computing has garnered significant attention for its biomimetic characteristics. However, as model sizes continue to expand and application workloads become increasingly diverse, it has emerged as a critical challenge to achieve efficient task deployment and system integration of neuromorphic acceleration hardware under the strict area and power constraints of edge AI. To address this challenge, we propose a heterogeneous neuromorphic system that tightly couples a neuromorphic array with a RISC-V CPU, enabling dynamic reconfigurable computing. The array consists of 16 cores equipped with ping-pong buffers and employs a dual Networks-on-Chip (NoC) architecture: a mesh NoC for spike and control data and a tree NoC for configuration. This design allows computation and configuration to be scheduled in parallel under the control of extended neuromorphic instructions. Furthermore, Delta Compressed Sparse Row (D-CSR) weight storage, together with Diagonal-Reuse Mapping (DRM) and the high-bandwidth Tree NoC, dramatically reduces configuration time while effectively addressing hardware challenges associated with configuration bottleneck. Implemented on Xilinx XCVU13P FPGA, the system achieves a peak performance of 72.4 GSOPS/s and an energy efficiency of 22.6 GSOPS/W for 8-bit weight. Verified through different Spiking Neural Networks (SNNs) deployment, this system with Dynamic Reconfigurable Computing increases the computation-to-total latency ratio and reduces network task latency greatly, and achieves an accuracy of 98.9 % on MNIST and 91.3 % on CIFAR-10.

神经形态计算因其仿生特性而受到广泛关注。然而，随着模型规模的不断扩大和应用工作负载的日益多样化，如何在边缘人工智能严格的面积和功率限制下实现神经形态加速硬件的高效任务部署和系统集成已成为一个关键挑战。为了解决这一挑战，我们提出了一种异构神经形态系统，该系统将神经形态阵列与RISC-V CPU紧密耦合，实现动态可重构计算。该阵列由16个配备乒乓球缓冲的核心组成，并采用双片上网络（NoC）架构：用于峰值和控制数据的网状NoC和用于配置的树状NoC。这种设计允许在扩展神经形态指令的控制下并行调度计算和配置。此外，Delta压缩稀疏行（D-CSR）权重存储，以及对角线重用映射（DRM）和高带宽树NoC，大大减少了配置时间，同时有效地解决了与配置瓶颈相关的硬件挑战。该系统在Xilinx XCVU13P FPGA上实现，在8位重量下，峰值性能为72.4 GSOPS/s，能效为22.6 GSOPS/W。通过不同的峰值神经网络（snn）部署验证，该系统具有动态可重构计算（Dynamic Reconfigurable Computing），大大提高了计算与总延迟比，降低了网络任务延迟，在MNIST和CIFAR-10上的准确率分别达到98.9%和91.3%。

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引用次数: 0

A compact SCR structure with reduced trigger voltage and parasitic capacitance for high-speed I/O ESD protection 紧凑的可控硅结构，降低触发电压和寄生电容，用于高速I/O ESD保护

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2025-12-04 DOI: 10.1016/j.mejo.2025.107003

Longhua Lin , Shupeng Chen , Ruibo Chen , Zhengwei Zhang , Hongxia Liu , Feibo Du , Zhiwei Liu

In this paper, a novel floating-base silicon-controlled rectifier (FBSCR) structure is proposed for low-voltage and high-speed I/O electrostatic discharge (ESD) protection. By incorporating a floating-base P-type transistor as its trigger element, the FBSCR enables avalanche breakdown to occur at a lower collector-emitter breakdown voltage and achieves a lower trigger voltage. Furthermore, by eliminating the N-type tap in the N-well, the parasitic capacitance between the anode and cathode is effectively mitigated. Transmission line pulse (TLP) and C-V measurements demonstrate that the FBSCR achieves ∼49 % reduction in trigger voltage and ∼43 % reduction in parasitic capacitance compared to the conventional low-voltage triggered SCR (LVTSCR). In addition, by the modulation of lateral parameters, the FBSCR exhibits excellent design flexibility to meet diverse specifications.

本文提出了一种新颖的浮基可控硅（FBSCR）结构，用于低压高速I/O静电放电（ESD）保护。通过采用浮动基极p型晶体管作为触发元件，FBSCR能够在较低的集电极-发射极击穿电压下发生雪崩击穿，并实现较低的触发电压。此外，通过消除n阱中的n型抽头，有效地减轻了阳极和阴极之间的寄生电容。传输线脉冲（TLP）和C-V测量表明，与传统的低压触发SCR （LVTSCR）相比，FBSCR的触发电压降低了49%，寄生电容降低了43%。此外，通过对横向参数的调制，FBSCR具有良好的设计灵活性，可以满足各种规格的要求。

引用次数: 0

Electrostatic discharge power-rail clamp circuit with silicon-controlled rectifier and MOSFET hybrid clamping device 采用可控硅整流器和MOSFET混合箝位装置的静电放电电源轨箝位电路

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2025-12-02 DOI: 10.1016/j.mejo.2025.107008

Yaping Yue , Ruizhen Wu , Ronghui Hou , Yuan Yang

Power-rail clamp circuit is an indispensable part of the whole-chip electrostatic discharge (ESD) protection architecture. It typically employs a controlled big MOSFET as the main clamping device, featuring a fast turn-on speed. However, silicon-controlled rectifier (SCR) device exhibits a significantly higher current-carrying capability per unit area compared to the MOSFET. In this paper, an ESD power-rail clamp circuit with SCR and MOSFET hybrid clamping device is proposed and verified by silicon. The SCR device is incorporated in the detection circuit to save layout area, a special amplifier is added to accelerate the turn-on and to elevate the holding voltage. Experimental results demonstrate that the proposed clamp circuit achieves higher failure current and faster turn-on speed compared to conventional designs.

电源轨箝位电路是全芯片静电放电（ESD）保护体系结构中不可缺少的组成部分。它通常采用受控的大型MOSFET作为主箝位器件，具有快速的导通速度。然而，与MOSFET相比，硅控整流器（SCR）器件表现出更高的单位面积载流能力。本文提出了一种具有可控硅和MOSFET混合箝位器件的ESD电源轨箝位电路，并用硅进行了验证。在检测电路中加入可控硅器件以节省布局面积，并增加专用放大器以加速导通和提高保持电压。实验结果表明，与传统电路相比，该电路具有更高的失效电流和更快的导通速度。

引用次数: 0

Design and verification of a robust near-memory computing architecture for image fusion tasks 图像融合任务的鲁棒近内存计算架构设计与验证

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2025-12-02 DOI: 10.1016/j.mejo.2025.107006

Aibin Yan , Han Bao , Jiaxun Cui , Haroon Waris , Jinpeng Li , Xiaoqing Wen , Fellow, IEEE

With the development of data-intensive applications, traditional von-Neumann architectures face the “storage wall” bottleneck, limiting the performance and energy efficiency of computing systems. Near-memory computing (NMC) mitigates this problem by integrating compute units near memory, enabling data to be processed in-situ. In this study, a novel near-memory computing architecture is designed and applied to the image fusion tasks with an approximate full adder. By integrating basic compute units near the storage module, local data-weighted processing reduces the performance-aware overhead of data migration. Experimental results show that, the designed approximate full adder reduces power consumption, delay and power-area-delay product (PADP) by an average of 4.3 %, 95.29 % and 94.49 %, respectively. Compared with the traditional von-Neumann architecture, the performance of the designed near-memory computing architecture is improved by 40 %. This solution realizes the energy efficiency optimization while maintaining the integrity of image fusion functionality, validating the feasibility of near-memory computing in lightweight image processing tasks.

随着数据密集型应用的发展，传统的冯-诺伊曼架构面临着“存储墙”的瓶颈，限制了计算系统的性能和能效。近内存计算（NMC）通过在内存附近集成计算单元，使数据能够就地处理，从而缓解了这一问题。本文设计了一种新的近内存计算架构，并将其应用于近似全加法器的图像融合任务。通过在存储模块附近集成基本计算单元，本地数据加权处理减少了数据迁移的性能开销。实验结果表明，所设计的近似全加法器的功耗、延迟和功率-面积延迟积（PADP）平均分别降低4.3%、95.29%和94.49%。与传统的冯-诺伊曼架构相比，所设计的近内存计算架构的性能提高了40%。该解决方案在保持图像融合功能完整性的同时实现了能效优化，验证了近内存计算在轻量级图像处理任务中的可行性。

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引用次数: 0

Withdrawal notice to “A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator” [Microelectron. J. 166 (2025) 106872] 关于“带同步四输出相位插补器的56 Gb/s PAM4斜率采样CDR”的撤销通知[微电子]。J. 166 (2025) 106872]

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2025-12-01 DOI: 10.1016/j.mejo.2025.106946

Zekai Yang , Xiaoteng Zhao , Huajin Sun , Xianting Su , Zhicheng Dong , Yilong Dong , Yukui Yu , Hongzhi Liang , Shubin Liu

引用次数: 0

Error-flagging assisted BCH decoder with compressed finite field traversal for STT-MRAM controllers 错误标记辅助BCH解码器与压缩有限场遍历STT-MRAM控制器

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal

Pub Date : 2025-12-01 DOI: 10.1016/j.mejo.2025.107005

Yongliang Zhou , Xun Wu , Beibei Zhang , Weizhe Tan , Chunyu Peng , Xiulong Wu

This paper proposes a hardware-optimized encoder/decoder implementation for 3-bit error-correcting BCH(63,45,3) codes, achieving significant improvements in decoding throughput, energy efficiency, and low hardware complexity through algorithmic enhancements and hardware architecture co-optimization. Three critical innovations are introduced: An error-flagging mechanism narrows the Chien search scope by prioritizing reliability-tagged bits; A hybrid lookup-table-and-logarithm-based finite field arithmetic unit is designed to optimize resource utilization for efficient Galois field GF(

2^{6}

) operations; An enhanced pipelined error-locator polynomial solver is developed with iterative coefficient adjustment capabilities to resolve underdetermined error patterns. The proposed detection scheme is designed using 28-nm CMOS technology and validated on a 256

\times

64 MRAM. Simulation results confirm the scheme’s ability to fully correct 3-bit errors and perform degraded detection for beyond-capacity errors, demonstrating a 24% improvement in energy efficiency compared to a conventional BCH decoder. These advantages render it highly suitable for flash-based STT-MRAM memory controllers, where high storage density and energy efficiency are paramount, as well as for low-power wireless communication systems.

本文提出了一种针对3位纠错BCH（63,45,3）码的硬件优化编码器/解码器实现，通过算法增强和硬件架构协同优化，显著提高了译码吞吐量、能源效率和低硬件复杂度。介绍了三个关键的创新：错误标记机制通过优先考虑可靠性标记的比特来缩小Chien的搜索范围；设计了一种基于查找表和对数的混合有限域算法单元，以优化资源利用，实现高效的伽罗瓦域GF（26）操作；提出了一种改进的流水线式误差定位多项式求解器，具有迭代系数调整能力，可用于求解欠确定的误差模式。该检测方案采用28纳米CMOS技术设计，并在256 × 64 MRAM上进行了验证。仿真结果证实了该方案能够完全纠正3位错误，并对超出容量的错误进行降级检测，与传统的BCH解码器相比，能效提高了24%。这些优点使其非常适合基于闪存的STT-MRAM存储器控制器，其中高存储密度和能源效率至关重要，以及低功耗无线通信系统。

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引用次数: 0

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