Pub Date : 2025-03-07DOI: 10.1016/j.mejo.2025.106639
Liang Tian, Qingchun Zhang
This paper presents a novel deep trench-type SiC MOSFET integrated with Schottky diodes (DT-JMOS) designed to improve oxide reliability and switching performances. In contrast to conventional SiC trench MOSFET with Schottky diodes (CT-JMOS), the DT-JMOS utilizes a narrower JFET region and a P-bot structure, resulting in superior electric field reductions in gate oxide layer to improve reliability. The unique structure also enables double-channel operation and deeper embedded Schottky contacts, significantly enhancing the current conduction capabilities in both the first and third quadrants. Furthermore, simulation results indicate that the DT-JMOS achieves a 97.6 % decrease in gate-to-drain capacitance (Cgd), leading to a 67.5 % improvement in gate-to-drain charge (Qgd), and eventually resulting in reductions by factors of 3.2 and 3.5 for figure of merit Qgd × Ron,sp and total switching losses (Etotal), respectively. These attributes suggest that the DT-JMOS is more suitable for high-voltage and high-frequency applications.
{"title":"A deep trench-type SiC MOSFET integrated with Schottky diode for enhanced oxide reliability and switching performances","authors":"Liang Tian, Qingchun Zhang","doi":"10.1016/j.mejo.2025.106639","DOIUrl":"10.1016/j.mejo.2025.106639","url":null,"abstract":"<div><div>This paper presents a novel deep trench-type SiC MOSFET integrated with Schottky diodes (DT-JMOS) designed to improve oxide reliability and switching performances. In contrast to conventional SiC trench MOSFET with Schottky diodes (CT-JMOS), the DT-JMOS utilizes a narrower JFET region and a P-bot structure, resulting in superior electric field reductions in gate oxide layer to improve reliability. The unique structure also enables double-channel operation and deeper embedded Schottky contacts, significantly enhancing the current conduction capabilities in both the first and third quadrants. Furthermore, simulation results indicate that the DT-JMOS achieves a 97.6 % decrease in gate-to-drain capacitance (<em>C</em><sub>gd</sub>), leading to a 67.5 % improvement in gate-to-drain charge (<em>Q</em><sub>gd</sub>), and eventually resulting in reductions by factors of 3.2 and 3.5 for figure of merit <em>Q</em><sub>gd</sub> × <em>R</em><sub>on,sp</sub> and total switching losses (<em>E</em><sub>total</sub>), respectively. These attributes suggest that the DT-JMOS is more suitable for high-voltage and high-frequency applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106639"},"PeriodicalIF":1.9,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143577946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-07DOI: 10.1016/j.mejo.2025.106637
Jen-Chieh Liu , Jian-Sheng Li , Yan-Xun Chen , Yu-Lung Lo
This study designs a vernier ring oscillator (VRO)-based time-to-digital converter (TDC), ensuring a proportional relationship between the timing resolutions of the coarse-tuning stage (CTS) and fine-tuning stage (FTS) under process, voltage, and temperature (PVT) variations. The design allows flexibility in extending the bit number to a wide input range during CTS. The timing resolutions of CTS and FTS were defined by the rise and fall times. Therefore, the timing ratio between CTS and FTS of VRO-based TDC remained constant under the PVT variations. This 14-bit TDC was fabricated using a 0.18 μm standard CMOS process with a core area of 45 μm × 200 μm. The measured timing resolution of the proposed VRO-based TDC was 125 ps, and the input range was from 10 to 200 ns. The DNL and INL values were less than ±0.244 and ± 0.336 LSB, respectively. The proposed VRO-based TDC was also integrated with a light sensor for Internet of Things applications.
{"title":"A VRO-based TDC with a constant timing resolution ratio between coarse-tuning and fine-tuning stages for a light sensor application","authors":"Jen-Chieh Liu , Jian-Sheng Li , Yan-Xun Chen , Yu-Lung Lo","doi":"10.1016/j.mejo.2025.106637","DOIUrl":"10.1016/j.mejo.2025.106637","url":null,"abstract":"<div><div>This study designs a vernier ring oscillator (VRO)-based time-to-digital converter (TDC), ensuring a proportional relationship between the timing resolutions of the coarse-tuning stage (CTS) and fine-tuning stage (FTS) under process, voltage, and temperature (PVT) variations. The design allows flexibility in extending the bit number to a wide input range during CTS. The timing resolutions of CTS and FTS were defined by the rise and fall times. Therefore, the timing ratio between CTS and FTS of VRO-based TDC remained constant under the PVT variations. This 14-bit TDC was fabricated using a 0.18 μm standard CMOS process with a core area of 45 μm × 200 μm. The measured timing resolution of the proposed VRO-based TDC was 125 ps, and the input range was from 10 to 200 ns. The DNL and INL values were less than ±0.244 and ± 0.336 LSB, respectively. The proposed VRO-based TDC was also integrated with a light sensor for Internet of Things applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106637"},"PeriodicalIF":1.9,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143592900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P-GaN high electron mobility transistor (HEMT) is currently the most commonly used enhanced GaN HEMT device. However, due to the presence of defects and traps, as well as the strong self-heating effect, p-GaN HEMT faces challenges with low breakdown voltage and poor device stability. In this study, a p-GaN HEMT structure via partially etched AlGaN has been proposed. The electrical and thermal performances of this device are thoroughly characterized and compared with conventional p-GaN HEMT. Through the proposed device structure, the breakdown voltage is increased from 290 V to 480 V, representing a 65 % improvement compared to conventional HEMT fabricated on the same wafer. The self-heating effect is also suppressed, resulting in a temperature reduction of 41.76 °C at a power level of 3.48 W. And more distinct temperature contrast images are obtained through thermoreflectance thermal imaging technology. This study provides a potential solution for fully leveraging the performance of p-GaN HEMT devices.
{"title":"Enhanced performance of p-GaN HEMT via partial etched AlGaN","authors":"Qingxin Liu , Shuang Wu , Kailin Ren , Luqiao Yin , Jianhua Zhang","doi":"10.1016/j.mejo.2025.106627","DOIUrl":"10.1016/j.mejo.2025.106627","url":null,"abstract":"<div><div>P-GaN high electron mobility transistor (HEMT) is currently the most commonly used enhanced GaN HEMT device. However, due to the presence of defects and traps, as well as the strong self-heating effect, p-GaN HEMT faces challenges with low breakdown voltage and poor device stability. In this study, a p-GaN HEMT structure via partially etched AlGaN has been proposed. The electrical and thermal performances of this device are thoroughly characterized and compared with conventional p-GaN HEMT. Through the proposed device structure, the breakdown voltage is increased from 290 V to 480 V, representing a 65 % improvement compared to conventional HEMT fabricated on the same wafer. The self-heating effect is also suppressed, resulting in a temperature reduction of 41.76 °C at a power level of 3.48 W. And more distinct temperature contrast images are obtained through thermoreflectance thermal imaging technology. This study provides a potential solution for fully leveraging the performance of p-GaN HEMT devices.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106627"},"PeriodicalIF":1.9,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143577538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-05DOI: 10.1016/j.mejo.2025.106630
Yansen Liu , Xiaonian Liu , Ying Zhou , Peng Cao
The Fin Field-Effect Transistor (FinFET) plays a crucial role in integrated circuits due to its superior control capabilities and low leakage current. However, its complex structure often leads to substantial computational demands and significant time consumption during Technology Computer-Aided Design (TCAD) simulations. To address these challenges, we innovatively propose a synchronous TCAD device simulation model based on Artificial Neural Network (ANN) for FinFET at advanced technology nodes, abbreviated as S-ANN. This model systematically extracts FinFET characteristics under various physical sizes and bias conditions from TCAD simulations and further analyzes transient response data contained in TDR files to build a training dataset, thereby enabling effective training of the S-ANN model. Through rigorous testing and evaluation, S-ANN has demonstrated high compatibility with Sentaurus TCAD and the capability to accurately simulate TCAD electrical characteristics. In addition, Nanosheet FET was used to verified the generalization capability of the S-ANN model. Compared to traditional TCAD simulations, the S-ANN model significantly reduces both computational resource usage and simulation time, while effectively overcoming convergence problems. This advancement offers strong support for the rapid design and optimization of advanced semiconductor devices.
{"title":"S-ANN: Synchronous TCAD device simulation of FinFET using Artificial Neural Network","authors":"Yansen Liu , Xiaonian Liu , Ying Zhou , Peng Cao","doi":"10.1016/j.mejo.2025.106630","DOIUrl":"10.1016/j.mejo.2025.106630","url":null,"abstract":"<div><div>The Fin Field-Effect Transistor (FinFET) plays a crucial role in integrated circuits due to its superior control capabilities and low leakage current. However, its complex structure often leads to substantial computational demands and significant time consumption during Technology Computer-Aided Design (TCAD) simulations. To address these challenges, we innovatively propose a synchronous TCAD device simulation model based on Artificial Neural Network (ANN) for FinFET at advanced technology nodes, abbreviated as S-ANN. This model systematically extracts FinFET characteristics under various physical sizes and bias conditions from TCAD simulations and further analyzes transient response data contained in TDR files to build a training dataset, thereby enabling effective training of the S-ANN model. Through rigorous testing and evaluation, S-ANN has demonstrated high compatibility with Sentaurus TCAD and the capability to accurately simulate TCAD electrical characteristics. In addition, Nanosheet FET was used to verified the generalization capability of the S-ANN model. Compared to traditional TCAD simulations, the S-ANN model significantly reduces both computational resource usage and simulation time, while effectively overcoming convergence problems. This advancement offers strong support for the rapid design and optimization of advanced semiconductor devices.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106630"},"PeriodicalIF":1.9,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143577945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-04DOI: 10.1016/j.mejo.2025.106622
Binjie Shi , Zhenglin Li , Hao Fang , Jiadong Li
The issue of high power consumption in the standby state of the driver chip for conventional LED is addressed by proposing an adjustable LDO. This LDO optimizes the static power consumption current of the LED driver chip through a power management circuit. In standby mode, a portion of the LDO circuit and the driver chip display circuit are deactivated, effectively reducing the static power consumption current of the driver chip. The standby mode static power consumption current of the LED driver chip equipped with adjustable LDO is measured to be 46.82μA, while the static power consumption current of the LED driver chip without adjustable LDO amounts to 151.83μA. In standby mode, compared to the non-adjustable option, there is a reduction of 105μA in adjustable power consumption current, with a corresponding static power consumption of only 0.23 mW for the LED driver chip. The LED driver chip designed in this paper is realized using a 180 nm BCD process.
{"title":"Design of a low power LED driver with adjustable LDO","authors":"Binjie Shi , Zhenglin Li , Hao Fang , Jiadong Li","doi":"10.1016/j.mejo.2025.106622","DOIUrl":"10.1016/j.mejo.2025.106622","url":null,"abstract":"<div><div>The issue of high power consumption in the standby state of the driver chip for conventional LED is addressed by proposing an adjustable LDO. This LDO optimizes the static power consumption current of the LED driver chip through a power management circuit. In standby mode, a portion of the LDO circuit and the driver chip display circuit are deactivated, effectively reducing the static power consumption current of the driver chip. The standby mode static power consumption current of the LED driver chip equipped with adjustable LDO is measured to be 46.82μA, while the static power consumption current of the LED driver chip without adjustable LDO amounts to 151.83μA. In standby mode, compared to the non-adjustable option, there is a reduction of 105μA in adjustable power consumption current, with a corresponding static power consumption of only 0.23 mW for the LED driver chip. The LED driver chip designed in this paper is realized using a 180 nm BCD process.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106622"},"PeriodicalIF":1.9,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143562044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-02DOI: 10.1016/j.mejo.2025.106617
Yaping Yue , Shi Pu , Ruizhen Wu , Ronghui Hou
Power-rail clamp circuit is crucial for the whole-chip electrostatic discharge (ESD) protection. In this paper, a new power-rail clamp circuit for on-chip ESD protection is proposed and verified by silicon. A dedicated false-triggering suppression circuit is introduced to make sure that the proposed clamp circuit keeps off during fast power-up events. By skillfully incorporating slew rate and voltage detection mechanisms are, offering a low clamp voltage and a reliable turn-off functionality. Experimental results from fabricated silicon die verify that the proposed clamp circuit exhibits high immunity to false triggering, making it suitable for robust ESD protection. Comparisons with the traditional solution are also presented.
{"title":"A new power-rail clamp circuit for on-chip electrostatic discharge protection","authors":"Yaping Yue , Shi Pu , Ruizhen Wu , Ronghui Hou","doi":"10.1016/j.mejo.2025.106617","DOIUrl":"10.1016/j.mejo.2025.106617","url":null,"abstract":"<div><div>Power-rail clamp circuit is crucial for the whole-chip electrostatic discharge (ESD) protection. In this paper, a new power-rail clamp circuit for on-chip ESD protection is proposed and verified by silicon. A dedicated false-triggering suppression circuit is introduced to make sure that the proposed clamp circuit keeps off during fast power-up events. By skillfully incorporating slew rate and voltage detection mechanisms are, offering a low clamp voltage and a reliable turn-off functionality. Experimental results from fabricated silicon die verify that the proposed clamp circuit exhibits high immunity to false triggering, making it suitable for robust ESD protection. Comparisons with the traditional solution are also presented.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106617"},"PeriodicalIF":1.9,"publicationDate":"2025-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143549258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-01DOI: 10.1016/j.mejo.2025.106620
Qiang Zhou , Sirui Peng , Taoran Shen , Jie Yin , Tieli Sun , Xiaoyong Xue
Deep learning has revolutionized numerous domains, creating an urgent need for storage systems capable of handling massive datasets and the intensive computational demands inherent to these workloads. Solid-State Drives (SSDs), known for their fast random access, low power consumption, and shock resistance, have emerged as a preferred storage medium in this context. However, traditional SSDs face critical challenges, including garbage collection (GC) overhead, write amplification, and inefficiencies in the software storage stack, stemming from the intrinsic characteristics of NAND flash and limitations in the existing storage ecosystem. These challenges underscore the necessity for specialized SSD controller chip designs tailored for deep learning workloads, addressing performance bottlenecks and optimizing data management to meet the unique demands of AI-driven applications. In this work, we implemented an open-channel SSD (OCSSD) based on a Xilinx FPGA, which can effectively alleviate the above-mentioned issues by exposing the structural characteristics of NAND flash to the host. To mitigate the performance cliff of I/O requests during GC operations, the link distance for data transmission is shortened by decoupling the host end and the device end. Moreover, the valid data migration and the GC operation frequency are both dramatically reduced by detecting and separating hot data and cold data to improve the overall performance of the SSD system. To verify the superiority of our design, we build a test platform through hardware and software co-design. The experimental results show that random read and random write bandwidth are increased by 159.7 % and 25.3 % compared to the mainstream SSDs, respectively. The latency of a single GC operation is reduced by an average of 12.64 % and the GC frequency is lowered by up to 64.8 %.
{"title":"Garbage collection optimization with data separation for large data storage in deep learning applications","authors":"Qiang Zhou , Sirui Peng , Taoran Shen , Jie Yin , Tieli Sun , Xiaoyong Xue","doi":"10.1016/j.mejo.2025.106620","DOIUrl":"10.1016/j.mejo.2025.106620","url":null,"abstract":"<div><div>Deep learning has revolutionized numerous domains, creating an urgent need for storage systems capable of handling massive datasets and the intensive computational demands inherent to these workloads. Solid-State Drives (SSDs), known for their fast random access, low power consumption, and shock resistance, have emerged as a preferred storage medium in this context. However, traditional SSDs face critical challenges, including garbage collection (GC) overhead, write amplification, and inefficiencies in the software storage stack, stemming from the intrinsic characteristics of NAND flash and limitations in the existing storage ecosystem. These challenges underscore the necessity for specialized SSD controller chip designs tailored for deep learning workloads, addressing performance bottlenecks and optimizing data management to meet the unique demands of AI-driven applications. In this work, we implemented an open-channel SSD (OCSSD) based on a Xilinx FPGA, which can effectively alleviate the above-mentioned issues by exposing the structural characteristics of NAND flash to the host. To mitigate the performance cliff of I/O requests during GC operations, the link distance for data transmission is shortened by decoupling the host end and the device end. Moreover, the valid data migration and the GC operation frequency are both dramatically reduced by detecting and separating hot data and cold data to improve the overall performance of the SSD system. To verify the superiority of our design, we build a test platform through hardware and software co-design. The experimental results show that random read and random write bandwidth are increased by 159.7 % and 25.3 % compared to the mainstream SSDs, respectively. The latency of a single GC operation is reduced by an average of 12.64 % and the GC frequency is lowered by up to 64.8 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106620"},"PeriodicalIF":1.9,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143549259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High speed communication networks depend on higher data rates for bandwidth expansion, but face challenges in maintaining signal integrity when data rates exceed 100 Gb/s due to ISI and reflection, which hinder transmission speed advancements. This paper proposes the design of an adaptive reflection cancellation circuit for high-speed 4-level pulse amplitude (PAM4) serializer-deserializer (Serdes) receiver based on analog-to-digital converter (ADC) + digital signal processing (DSP) architecture. The proposed parallel Floating Tap Feedforward equalization(FT-FFE) effectively mitigates the impact of reflection without the need for a large number of equalizers, thereby reducing power consumption overhead. A Loop-Refactored decision feedback equalizer (LR-DFE) is implemented to mitigate timing constraints in ADC-DSP based high-speed wireline receivers, improving system performance and timing reliability. The tap coefficients are adaptively updated in combination with the Least Mean Square (LMS) algorithm. Simulation and FPGA platform validation results demonstrate that at a data rate of 56 Gb/s, the bit error rate(BER) is below 1e-12 through a channel with 39 dB insertion loss(IL).
{"title":"A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver","authors":"Cewen Liu , Xingyun Qi , Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai","doi":"10.1016/j.mejo.2025.106612","DOIUrl":"10.1016/j.mejo.2025.106612","url":null,"abstract":"<div><div>High speed communication networks depend on higher data rates for bandwidth expansion, but face challenges in maintaining signal integrity when data rates exceed 100 Gb/s due to ISI and reflection, which hinder transmission speed advancements. This paper proposes the design of an adaptive reflection cancellation circuit for high-speed 4-level pulse amplitude (PAM4) serializer-deserializer (Serdes) receiver based on analog-to-digital converter (ADC) + digital signal processing (DSP) architecture. The proposed parallel Floating Tap Feedforward equalization(FT-FFE) effectively mitigates the impact of reflection without the need for a large number of equalizers, thereby reducing power consumption overhead. A Loop-Refactored decision feedback equalizer (LR-DFE) is implemented to mitigate timing constraints in ADC-DSP based high-speed wireline receivers, improving system performance and timing reliability. The tap coefficients are adaptively updated in combination with the Least Mean Square (LMS) algorithm. Simulation and FPGA platform validation results demonstrate that at a data rate of 56 Gb/s, the bit error rate(BER) is below 1e-12 through a channel with 39 dB insertion loss(IL).</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106612"},"PeriodicalIF":1.9,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143562046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A approach to achieving compactness and performance enhancement in lowpass filter (LPF) is described in this work. By leveraging the parasitic inductance of metal interconnects as inductive components, the proposed approach significantly reduces the overall size of the filter. Additionally, the combined effect of parasitic inductance and source-load coupling parasitic capacitance is utilized to create multiple transmission zeros, leading to improved isolation and wider bandwidth. Furthermore, a port fusion technique is introduced, which reduces the number of ports, minimizing interconnect losses and further enhancing compactness. The proposed LPF occupies a compact space of 0.31 × 0.34 mm2, features a cut-off frequency of 6.31 GHz, achieves an insertion loss of 30 dB at 30 GHz, and maintains a return loss below 0.4 dB.
{"title":"Parasitic-induced multi-zero generation and port-fusion compact filter based on 3-D through-silicon via technology","authors":"Xiangkun Yin, Xiangyu Ma, Nairong Liu, Libo Qian, Tao Zhang, Qijun Lu, Zhangming Zhu","doi":"10.1016/j.mejo.2025.106618","DOIUrl":"10.1016/j.mejo.2025.106618","url":null,"abstract":"<div><div>A approach to achieving compactness and performance enhancement in lowpass filter (LPF) is described in this work. By leveraging the parasitic inductance of metal interconnects as inductive components, the proposed approach significantly reduces the overall size of the filter. Additionally, the combined effect of parasitic inductance and source-load coupling parasitic capacitance is utilized to create multiple transmission zeros, leading to improved isolation and wider bandwidth. Furthermore, a port fusion technique is introduced, which reduces the number of ports, minimizing interconnect losses and further enhancing compactness. The proposed LPF occupies a compact space of 0.31 × 0.34 mm<sup>2</sup>, features a cut-off frequency of 6.31 GHz, achieves an insertion loss of 30 dB at 30 GHz, and maintains a return loss below 0.4 dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106618"},"PeriodicalIF":1.9,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143520968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-27DOI: 10.1016/j.mejo.2025.106613
Lianzhen Zhang, Haipeng Fu, Lang Nie, Zhipeng Wang, Hao Shi, Kaixue Ma
In this paper, a wide tuning range low phase noise (PN) voltage controlled oscillator (VCO) is proposed which incorporates three switchable Class-F23 VCO cores. In order to solve the problems of output power degradation and divider error due to charge leakage between cores, a multi-core switching control (MCSC) technology is proposed. This technology enables flexible control of multiple cores operation and improves the isolation between cores. To achieve low PN over a wide tuning range, F23 VCO cores based on fourth-order transformer and second harmonic filtering network are designed. The VCO is fabricated in a 130 nm SiGe BiCMOS technology and achieves a measured wide tuning range of 81% from 2.0 to 4.7 GHz. The measured PN at 1-MHz offset is from −124.8 dBc/Hz −134.4 dBc/Hz, with a peak FoMT of 200.8 dBc/Hz. The optimum flicker noise corner is around 100kHz, and the core area is 0.51 .
{"title":"A Switchable-core Wideband Class-F23 VCO with 200.8 dBc/Hz Peak FoMT in 130-nm SiGe","authors":"Lianzhen Zhang, Haipeng Fu, Lang Nie, Zhipeng Wang, Hao Shi, Kaixue Ma","doi":"10.1016/j.mejo.2025.106613","DOIUrl":"10.1016/j.mejo.2025.106613","url":null,"abstract":"<div><div>In this paper, a wide tuning range low phase noise (PN) voltage controlled oscillator (VCO) is proposed which incorporates three switchable Class-F<sub>23</sub> VCO cores. In order to solve the problems of output power degradation and divider error due to charge leakage between cores, a multi-core switching control (MCSC) technology is proposed. This technology enables flexible control of multiple cores operation and improves the isolation between cores. To achieve low PN over a wide tuning range, F<sub>23</sub> VCO cores based on fourth-order transformer and second harmonic filtering network are designed. The VCO is fabricated in a 130 nm SiGe BiCMOS technology and achieves a measured wide tuning range of 81% from 2.0 to 4.7 GHz. The measured PN at 1-MHz offset is from −124.8 dBc/Hz <span><math><mo>∼</mo></math></span> −134.4 dBc/Hz, with a peak FoMT of 200.8 dBc/Hz. The optimum flicker noise corner is around 100kHz, and the core area is 0.51 <span><math><msup><mrow><mtext>mm</mtext></mrow><mrow><mn>2</mn></mrow></msup></math></span>.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106613"},"PeriodicalIF":1.9,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143562045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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