A trench beside field limiting rings terminal for improved 4H-SiC junction barrier Schottky diodes: Proposal and investigation

IF 1.6 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics Reliability Pub Date : 2024-07-17 DOI:10.1016/j.microrel.2024.115459
Xiaofeng Ye , Huihuang Ke , Shubo Wei , Hongjin Weng , Xinwei Wang , Shen Yuong Wong , Weifeng Yang
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Abstract

A novel trench beside field limiting rings (TBFLR) terminal for 4H-SiC junction barrier Schottky (JBS) diodes is introduced and analyzed by technical computer-aided design (TCAD) simulation, addressing the electric field crowding challenge in high-voltage applications. The design parameters of the devices are optimized by striking a balance between forward and reverse electrical performances. Comparative analysis reveals that TBFLR significantly reduces the surface peak electric field, making it particularly advantageous for shallow-junction devices. Conversely, trench inside FLR (TFLR) is suited for deep-junction applications due to its deeper junction and higher breakdown voltage (BV). The TBFLR design excels with its low on-resistance and compact terminal length, especially in ultra-high voltage (>6500 V) scenarios, achieving target BV with fewer rings and reduced terminal area. Notably, the TBFLR has a terminal efficiency of at least 80 % while keeping trench depth within the 60 % range of the junction depth. Furthermore, an enhanced computational model is proposed, which introduces harmonic parameters to quantify the role of the trench in FLR, and this adaptable model can be effectively extended to the composite renewal of FLR structures. This work provides a distinct application strategy for trench-based FLR structures, significantly broadening the scope of terminal design possibilities.

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用于改进型 4H-SiC 结势垒肖特基二极管的场限制环终端旁的沟槽:建议与研究
介绍了一种用于 4H-SiC 结势垒肖特基(JBS)二极管的新型沟槽旁场限制环(TBFLR)端子,并通过技术计算机辅助设计(TCAD)仿真进行了分析,以解决高压应用中的电场拥挤难题。通过平衡正向和反向电气性能,优化了器件的设计参数。对比分析表明,TBFLR 能显著降低表面峰值电场,因此特别适用于浅结器件。相反,沟槽内 FLR (TFLR) 由于具有更深的结和更高的击穿电压 (BV),适合深结应用。TBFLR 设计具有低导通电阻和紧凑的端子长度等优点,尤其适用于超高电压(6500 V)应用,能以更少的环和更小的端子面积实现目标击穿电压。值得注意的是,TBFLR 的端子效率至少为 80%,同时沟槽深度保持在结深度的 60% 范围内。此外,我们还提出了一种增强型计算模型,该模型引入了谐波参数来量化沟槽在 FLR 中的作用,这种适应性强的模型可有效扩展到 FLR 结构的复合更新。这项工作为基于沟槽的 FLR 结构提供了一种独特的应用策略,大大拓宽了终端设计的可能性范围。
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来源期刊
Microelectronics Reliability
Microelectronics Reliability 工程技术-工程:电子与电气
CiteScore
3.30
自引率
12.50%
发文量
342
审稿时长
68 days
期刊介绍: Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.
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