A Pixel-Wise Segmentation Method for Automatic X-Ray Image Detection of Chip Packaging Defects

IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2024-07-15 DOI:10.1109/TCPMT.2024.3428595
Jie Wang;Gaomin Li;Yuezheng Zhou;Haoyu Bai;Xuan Li;Lijun Zhong;Xiaohu Zhang
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Abstract

Integrated circuit chips are the most common electronic components, and visual internal defect detection is essential for ensuring product quality following packaging. However, efficient detection of chip internal defects is challenging due to the complexity of the background and the faintness of defects. To overcome the above difficulties, a novel deep learning-based defect segmentation framework is proposed, which relies on an image preprocessing (IPP) scheme and a defect segmentation network (DSNet). The IPP is composed of a rotation correction algorithm and a region segmentation algorithm for removing the influence of background and obtaining chip packaging region. The DSNet is proposed to precisely and efficiently segment the internal defects. To address the scarcity of data and avoid overfitting, we proposed the lightweight convolution block by using depth-wise separable convolution (DWSC) to reduce the number of parameters. Besides, the attention gate (AG) module is incorporated into the skip connection to handle the shape varieties of the defects. Moreover, the Focal loss function is designed to guide the network to pay attention to small defects that are difficult to distinguish. The robustness and adaptability of the proposed method are evaluated on three typical types of chip X-ray datasets from real-world inspection lines. Experimental results show that the proposed framework achieves a satisfactory tradeoff between detection accuracy and speed with an $F1$ -score of 72.69% and a frames per second (FPS) of 17.5 on average, resulting in superior segmentation performance even with sparse or insufficient data.
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用于自动检测芯片封装缺陷的 X 射线图像像素分割方法
集成电路芯片是最常见的电子元件,可视内部缺陷检测对于确保封装后的产品质量至关重要。然而,由于背景的复杂性和缺陷的模糊性,高效检测芯片内部缺陷具有挑战性。为了克服上述困难,本文提出了一种基于深度学习的新型缺陷分割框架,该框架依赖于图像预处理(IPP)方案和缺陷分割网络(DSNet)。IPP 由旋转校正算法和区域分割算法组成,用于去除背景影响并获得芯片封装区域。DSNet 用于精确有效地分割内部缺陷。针对数据稀缺和避免过拟合的问题,我们提出了轻量级卷积块,利用深度可分离卷积(DWSC)来减少参数数量。此外,在跳转连接中加入了注意门(AG)模块,以处理缺陷的形状变化。此外,还设计了焦点损失函数,以引导网络关注难以区分的小缺陷。我们在实际检测线的三种典型芯片 X 射线数据集上评估了所提方法的鲁棒性和适应性。实验结果表明,所提出的框架在检测精度和速度之间取得了令人满意的平衡,F1$ 分数为 72.69%,平均每秒帧数(FPS)为 17.5,即使在数据稀少或不足的情况下也能实现出色的分割性能。
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来源期刊
IEEE Transactions on Components, Packaging and Manufacturing Technology
IEEE Transactions on Components, Packaging and Manufacturing Technology ENGINEERING, MANUFACTURING-ENGINEERING, ELECTRICAL & ELECTRONIC
CiteScore
4.70
自引率
13.60%
发文量
203
审稿时长
3 months
期刊介绍: IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.
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