Jie Wang;Gaomin Li;Yuezheng Zhou;Haoyu Bai;Xuan Li;Lijun Zhong;Xiaohu Zhang
{"title":"A Pixel-Wise Segmentation Method for Automatic X-Ray Image Detection of Chip Packaging Defects","authors":"Jie Wang;Gaomin Li;Yuezheng Zhou;Haoyu Bai;Xuan Li;Lijun Zhong;Xiaohu Zhang","doi":"10.1109/TCPMT.2024.3428595","DOIUrl":null,"url":null,"abstract":"Integrated circuit chips are the most common electronic components, and visual internal defect detection is essential for ensuring product quality following packaging. However, efficient detection of chip internal defects is challenging due to the complexity of the background and the faintness of defects. To overcome the above difficulties, a novel deep learning-based defect segmentation framework is proposed, which relies on an image preprocessing (IPP) scheme and a defect segmentation network (DSNet). The IPP is composed of a rotation correction algorithm and a region segmentation algorithm for removing the influence of background and obtaining chip packaging region. The DSNet is proposed to precisely and efficiently segment the internal defects. To address the scarcity of data and avoid overfitting, we proposed the lightweight convolution block by using depth-wise separable convolution (DWSC) to reduce the number of parameters. Besides, the attention gate (AG) module is incorporated into the skip connection to handle the shape varieties of the defects. Moreover, the Focal loss function is designed to guide the network to pay attention to small defects that are difficult to distinguish. The robustness and adaptability of the proposed method are evaluated on three typical types of chip X-ray datasets from real-world inspection lines. Experimental results show that the proposed framework achieves a satisfactory tradeoff between detection accuracy and speed with an \n<inline-formula> <tex-math>$F1$ </tex-math></inline-formula>\n-score of 72.69% and a frames per second (FPS) of 17.5 on average, resulting in superior segmentation performance even with sparse or insufficient data.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 8","pages":"1520-1527"},"PeriodicalIF":2.3000,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Components, Packaging and Manufacturing Technology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10599315/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Integrated circuit chips are the most common electronic components, and visual internal defect detection is essential for ensuring product quality following packaging. However, efficient detection of chip internal defects is challenging due to the complexity of the background and the faintness of defects. To overcome the above difficulties, a novel deep learning-based defect segmentation framework is proposed, which relies on an image preprocessing (IPP) scheme and a defect segmentation network (DSNet). The IPP is composed of a rotation correction algorithm and a region segmentation algorithm for removing the influence of background and obtaining chip packaging region. The DSNet is proposed to precisely and efficiently segment the internal defects. To address the scarcity of data and avoid overfitting, we proposed the lightweight convolution block by using depth-wise separable convolution (DWSC) to reduce the number of parameters. Besides, the attention gate (AG) module is incorporated into the skip connection to handle the shape varieties of the defects. Moreover, the Focal loss function is designed to guide the network to pay attention to small defects that are difficult to distinguish. The robustness and adaptability of the proposed method are evaluated on three typical types of chip X-ray datasets from real-world inspection lines. Experimental results show that the proposed framework achieves a satisfactory tradeoff between detection accuracy and speed with an
$F1$
-score of 72.69% and a frames per second (FPS) of 17.5 on average, resulting in superior segmentation performance even with sparse or insufficient data.
期刊介绍:
IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.