Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3447124
Guoliao Sun;Wen Jing;Siyuan Lu;Cheng Peng;Wenhui Zhu;Liancheng Wang
The double-sided cooling (DSC) module introduces greater thermomechanical stress compared to single-sided cooling (SSC) modules, posing a significant threat to reliability. The manufacturing process is complex, requiring multiple sintering or reflow operations. Due to gravitational factors, this results in uneven thickness in the solder layer, further exacerbating the reliability issues. This article investigates the failure mechanism of the middle solder layer (SAC305) in flip-chip double-sided cooling (FCDSC) modules under thermal cycling conditions using a thermomechanical coupled model. The results indicate that when the solder layer tilt angle reaches 1.53°, the lifetime is reduced by 99.3%. Local viscoplastic strain in the solder at stress concentration areas is identified as a key factor in solder layer fatigue failure. Subsequent experiments confirm that fatigue cracks occur on the thinner side of the solder layer. There, the coarsening of the Ag3Sn eutectic phase is more severe, leading to reduced tensile strength, thus becoming a crack initiation site. Finally, the protrusions-spacer technique is proposed to control the evenness of the solder layer, with experiments demonstrating an average reduction in solder layer tilt by 79.7%.
{"title":"Failure Mechanism and Reliability Research of Solder Layer Tilt in Double-Sided Cooling Power Modules","authors":"Guoliao Sun;Wen Jing;Siyuan Lu;Cheng Peng;Wenhui Zhu;Liancheng Wang","doi":"10.1109/TCPMT.2024.3447124","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3447124","url":null,"abstract":"The double-sided cooling (DSC) module introduces greater thermomechanical stress compared to single-sided cooling (SSC) modules, posing a significant threat to reliability. The manufacturing process is complex, requiring multiple sintering or reflow operations. Due to gravitational factors, this results in uneven thickness in the solder layer, further exacerbating the reliability issues. This article investigates the failure mechanism of the middle solder layer (SAC305) in flip-chip double-sided cooling (FCDSC) modules under thermal cycling conditions using a thermomechanical coupled model. The results indicate that when the solder layer tilt angle reaches 1.53°, the lifetime is reduced by 99.3%. Local viscoplastic strain in the solder at stress concentration areas is identified as a key factor in solder layer fatigue failure. Subsequent experiments confirm that fatigue cracks occur on the thinner side of the solder layer. There, the coarsening of the Ag3Sn eutectic phase is more severe, leading to reduced tensile strength, thus becoming a crack initiation site. Finally, the protrusions-spacer technique is proposed to control the evenness of the solder layer, with experiments demonstrating an average reduction in solder layer tilt by 79.7%.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142551996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3471053
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Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3471051
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information","authors":"","doi":"10.1109/TCPMT.2024.3471051","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3471051","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10739383","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142555090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3484209
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Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3484225
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Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3471055
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Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3484219
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information","authors":"","doi":"10.1109/TCPMT.2024.3484219","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3484219","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10739376","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142555069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3484223
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors","authors":"","doi":"10.1109/TCPMT.2024.3484223","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3484223","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10739380","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142555089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-18DOI: 10.1109/TCPMT.2024.3462944
Jianyu Feng;Rong Fu;Yunqian Song;Qidong Wang;Chuan Chen;Liqiang Cao
The three-dimensional integration technology is an effective solution of extending Moore’s law, with better performance and higher density. However, the temperature rise caused by hot spots in 3-D integration will be more prominent. By extracting the equivalent thermal conductivity of the microbump layer and the chip with TSVs, the equivalent analytical model for detailed 3-D integration structure is proposed in this article. The accuracy of equivalence is verified using finite element simulation, and the model is used to calculate the thermal resistance and to predict the maximum temperature of the hot spot. In 3-D integration, the second conduction path can significantly reduce the temperature of the hot spot. A new analytical solution is proposed in this article for calculating thermal resistance and predicting the maximum temperature of the hot spot in 3-D integration. The results demonstrate that the thermal resistance network model proposed can precisely predict the temperature rise of the hot spot. For hot spots with different sizes, the error between simulation and network model is merely within $2~^{circ }$ C. The effects of different factors on the hotspot temperature rise in 3-D integration is investigated. As the chip material, diamond can significantly reduce the hotspot temperature. Furthermore, both the chip thickness and the thermal conductivity of microbump layer have effect on the temperature of hot spot with different sizes. For cases with large-sized hot spot, to decrease the hotspot temperature, smaller microbump and greater chip thickness are advised in packaging.
三维集成技术是扩展摩尔定律的有效解决方案，具有更好的性能和更高的密度。然而，三维集成中热点引起的温升问题会更加突出。本文通过提取微凸块层和带 TSV 芯片的等效热导率，提出了详细三维集成结构的等效分析模型。利用有限元仿真验证了等效的准确性，并利用该模型计算了热阻和预测了热点的最高温度。在三维集成中，第二传导路径可显著降低热点温度。本文提出了一种新的分析解决方案，用于计算热阻和预测三维集成中热点的最高温度。结果表明，所提出的热阻网络模型可以精确预测热点的温升。对于不同尺寸的热点，模拟与网络模型的误差仅在 2~^{circ }$ C 范围内。作为芯片材料，金刚石能显著降低热点温度。此外，芯片厚度和微凸块层的热导率都会对不同大小的热点温度产生影响。对于大尺寸热点的情况，为降低热点温度，建议在封装时采用更小的微凸块和更大的芯片厚度。
{"title":"The Analytical Model of Hotspot Temperature and the Effects of Different Factors in 3-D Integration","authors":"Jianyu Feng;Rong Fu;Yunqian Song;Qidong Wang;Chuan Chen;Liqiang Cao","doi":"10.1109/TCPMT.2024.3462944","DOIUrl":"10.1109/TCPMT.2024.3462944","url":null,"abstract":"The three-dimensional integration technology is an effective solution of extending Moore’s law, with better performance and higher density. However, the temperature rise caused by hot spots in 3-D integration will be more prominent. By extracting the equivalent thermal conductivity of the microbump layer and the chip with TSVs, the equivalent analytical model for detailed 3-D integration structure is proposed in this article. The accuracy of equivalence is verified using finite element simulation, and the model is used to calculate the thermal resistance and to predict the maximum temperature of the hot spot. In 3-D integration, the second conduction path can significantly reduce the temperature of the hot spot. A new analytical solution is proposed in this article for calculating thermal resistance and predicting the maximum temperature of the hot spot in 3-D integration. The results demonstrate that the thermal resistance network model proposed can precisely predict the temperature rise of the hot spot. For hot spots with different sizes, the error between simulation and network model is merely within \u0000<inline-formula> <tex-math>$2~^{circ }$ </tex-math></inline-formula>\u0000C. The effects of different factors on the hotspot temperature rise in 3-D integration is investigated. As the chip material, diamond can significantly reduce the hotspot temperature. Furthermore, both the chip thickness and the thermal conductivity of microbump layer have effect on the temperature of hot spot with different sizes. For cases with large-sized hot spot, to decrease the hotspot temperature, smaller microbump and greater chip thickness are advised in packaging.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142248860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Microbolometers are the core detectors of uncooled thermal sensors. These detectors require a high vacuum environment (<1> $sim 12times 12$ mm) wafer-level Cu-Sn SLID packages using a time-dependent cap deflection study and exposing them to humidity and thermal shock test environments. Cap deflection measurements at the wafer level indicate that the dies maintained a stable vacuum for more than 13 months after bonding before they were exposed to harsh environments. The Cu-Sn SLID packages display resilience to corrosion effects, with 93% of the dies passing the humidity test. In contrast, all dies failed the thermal shock test due to vertical cracks in the Cu/Cu3Sn/Cu bondline. These vertical cracks are primarily found to propagate through voids in the Cu3Sn, where the stresses are assumed to be the largest. To mitigate vertical crack formation and enhance long-term sealing frame integrity, void formation must be minimized. Strict requirements are thus put on the electroplating process to avoid contamination, demanding careful monitoring of the bath conditions and optimization of the electroplating parameters.
{"title":"Robustness of Large-Size Vacuum Sealed Packages for Microbolometer Array","authors":"Hexin Xia;Hoang-Vu Nguyen;Avisek Roy;Per Ohlckers;Knut Eilif Aasmundtveit","doi":"10.1109/TCPMT.2024.3462818","DOIUrl":"10.1109/TCPMT.2024.3462818","url":null,"abstract":"Microbolometers are the core detectors of uncooled thermal sensors. These detectors require a high vacuum environment (<1> <tex-math>$sim 12times 12$ </tex-math></inline-formula>\u0000 mm) wafer-level Cu-Sn SLID packages using a time-dependent cap deflection study and exposing them to humidity and thermal shock test environments. Cap deflection measurements at the wafer level indicate that the dies maintained a stable vacuum for more than 13 months after bonding before they were exposed to harsh environments. The Cu-Sn SLID packages display resilience to corrosion effects, with 93% of the dies passing the humidity test. In contrast, all dies failed the thermal shock test due to vertical cracks in the Cu/Cu3Sn/Cu bondline. These vertical cracks are primarily found to propagate through voids in the Cu3Sn, where the stresses are assumed to be the largest. To mitigate vertical crack formation and enhance long-term sealing frame integrity, void formation must be minimized. Strict requirements are thus put on the electroplating process to avoid contamination, demanding careful monitoring of the bath conditions and optimization of the electroplating parameters.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142248861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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