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Failure Mechanism and Reliability Research of Solder Layer Tilt in Double-Sided Cooling Power Modules 双面冷却电源模块焊层倾斜的失效机理与可靠性研究
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3447124
Guoliao Sun;Wen Jing;Siyuan Lu;Cheng Peng;Wenhui Zhu;Liancheng Wang
The double-sided cooling (DSC) module introduces greater thermomechanical stress compared to single-sided cooling (SSC) modules, posing a significant threat to reliability. The manufacturing process is complex, requiring multiple sintering or reflow operations. Due to gravitational factors, this results in uneven thickness in the solder layer, further exacerbating the reliability issues. This article investigates the failure mechanism of the middle solder layer (SAC305) in flip-chip double-sided cooling (FCDSC) modules under thermal cycling conditions using a thermomechanical coupled model. The results indicate that when the solder layer tilt angle reaches 1.53°, the lifetime is reduced by 99.3%. Local viscoplastic strain in the solder at stress concentration areas is identified as a key factor in solder layer fatigue failure. Subsequent experiments confirm that fatigue cracks occur on the thinner side of the solder layer. There, the coarsening of the Ag3Sn eutectic phase is more severe, leading to reduced tensile strength, thus becoming a crack initiation site. Finally, the protrusions-spacer technique is proposed to control the evenness of the solder layer, with experiments demonstrating an average reduction in solder layer tilt by 79.7%.
与单面冷却(SSC)模块相比,双面冷却(DSC)模块会产生更大的热机械应力,对可靠性构成重大威胁。制造工艺复杂,需要多次烧结或回流焊操作。由于重力因素,这会导致焊料层厚度不均匀,进一步加剧可靠性问题。本文利用热机械耦合模型研究了热循环条件下倒装芯片双面冷却(FCDSC)模块中中间焊接层(SAC305)的失效机理。结果表明,当焊接层倾斜角达到 1.53°时,寿命会缩短 99.3%。焊料中应力集中区域的局部粘塑性应变被认为是导致焊料层疲劳失效的关键因素。随后的实验证实,疲劳裂纹发生在焊料层较薄的一侧。在那里,Ag3Sn 共晶相的粗化更为严重,导致抗拉强度降低,从而成为裂纹的起始点。最后,我们提出了突起-垫片技术来控制焊料层的均匀度,实验表明焊料层倾斜度平均降低了 79.7%。
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information 电气和电子工程师学会《部件、封装和制造技术》期刊 出版信息
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3471051
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors IEEE 《部件、封装和制造技术》期刊 为作者提供的信息
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3471053
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Blank Page 空白页
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3484209
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IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information 电气和电子工程师学会《元件、封装和制造技术》学会信息
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3484225
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IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information 电气和电子工程师学会《元件、封装和制造技术》学会信息
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3471055
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IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors IEEE 《部件、封装和制造技术》期刊 为作者提供的信息
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3484223
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information 电气和电子工程师学会《部件、封装和制造技术》期刊 出版信息
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3484219
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引用次数: 0
The Analytical Model of Hotspot Temperature and the Effects of Different Factors in 3-D Integration 三维集成中热点温度的分析模型及不同因素的影响
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-09-18 DOI: 10.1109/TCPMT.2024.3462944
Jianyu Feng;Rong Fu;Yunqian Song;Qidong Wang;Chuan Chen;Liqiang Cao
The three-dimensional integration technology is an effective solution of extending Moore’s law, with better performance and higher density. However, the temperature rise caused by hot spots in 3-D integration will be more prominent. By extracting the equivalent thermal conductivity of the microbump layer and the chip with TSVs, the equivalent analytical model for detailed 3-D integration structure is proposed in this article. The accuracy of equivalence is verified using finite element simulation, and the model is used to calculate the thermal resistance and to predict the maximum temperature of the hot spot. In 3-D integration, the second conduction path can significantly reduce the temperature of the hot spot. A new analytical solution is proposed in this article for calculating thermal resistance and predicting the maximum temperature of the hot spot in 3-D integration. The results demonstrate that the thermal resistance network model proposed can precisely predict the temperature rise of the hot spot. For hot spots with different sizes, the error between simulation and network model is merely within $2~^{circ }$ C. The effects of different factors on the hotspot temperature rise in 3-D integration is investigated. As the chip material, diamond can significantly reduce the hotspot temperature. Furthermore, both the chip thickness and the thermal conductivity of microbump layer have effect on the temperature of hot spot with different sizes. For cases with large-sized hot spot, to decrease the hotspot temperature, smaller microbump and greater chip thickness are advised in packaging.
三维集成技术是扩展摩尔定律的有效解决方案,具有更好的性能和更高的密度。然而,三维集成中热点引起的温升问题会更加突出。本文通过提取微凸块层和带 TSV 芯片的等效热导率,提出了详细三维集成结构的等效分析模型。利用有限元仿真验证了等效的准确性,并利用该模型计算了热阻和预测了热点的最高温度。在三维集成中,第二传导路径可显著降低热点温度。本文提出了一种新的分析解决方案,用于计算热阻和预测三维集成中热点的最高温度。结果表明,所提出的热阻网络模型可以精确预测热点的温升。对于不同尺寸的热点,模拟与网络模型的误差仅在 2~^{circ }$ C 范围内。作为芯片材料,金刚石能显著降低热点温度。此外,芯片厚度和微凸块层的热导率都会对不同大小的热点温度产生影响。对于大尺寸热点的情况,为降低热点温度,建议在封装时采用更小的微凸块和更大的芯片厚度。
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Robustness of Large-Size Vacuum Sealed Packages for Microbolometer Array 用于微测辐射热计阵列的大型真空密封封装的稳健性
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-09-17 DOI: 10.1109/TCPMT.2024.3462818
Hexin Xia;Hoang-Vu Nguyen;Avisek Roy;Per Ohlckers;Knut Eilif Aasmundtveit
Microbolometers are the core detectors of uncooled thermal sensors. These detectors require a high vacuum environment (<1> $sim 12times 12$ mm) wafer-level Cu-Sn SLID packages using a time-dependent cap deflection study and exposing them to humidity and thermal shock test environments. Cap deflection measurements at the wafer level indicate that the dies maintained a stable vacuum for more than 13 months after bonding before they were exposed to harsh environments. The Cu-Sn SLID packages display resilience to corrosion effects, with 93% of the dies passing the humidity test. In contrast, all dies failed the thermal shock test due to vertical cracks in the Cu/Cu3Sn/Cu bondline. These vertical cracks are primarily found to propagate through voids in the Cu3Sn, where the stresses are assumed to be the largest. To mitigate vertical crack formation and enhance long-term sealing frame integrity, void formation must be minimized. Strict requirements are thus put on the electroplating process to avoid contamination, demanding careful monitoring of the bath conditions and optimization of the electroplating parameters.
微测辐射热计是非制冷热传感器的核心探测器。这些探测器需要在高真空环境(12 毫米)下使用晶圆级铜-锰 SLID 封装,使用随时间变化的电容偏转研究,并将其暴露在湿度和热冲击测试环境中。晶圆级瓶盖挠度测量结果表明,芯片在接合后保持稳定真空状态的时间超过 13 个月,然后才暴露在恶劣的环境中。铜-锰 SLID 封装显示出对腐蚀影响的适应能力,93% 的芯片通过了湿度测试。相反,由于 Cu/Cu3Sn/Cu 键合线出现垂直裂纹,所有模具都未能通过热冲击测试。这些垂直裂纹主要是通过 Cu3Sn 的空隙传播的,而此处的应力被认为是最大的。为了减少垂直裂纹的形成并提高密封框架的长期完整性,必须尽量减少空隙的形成。因此,对电镀工艺提出了严格的要求,以避免污染,这就要求对电镀槽条件进行仔细监控,并优化电镀参数。
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