Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3447124
Guoliao Sun;Wen Jing;Siyuan Lu;Cheng Peng;Wenhui Zhu;Liancheng Wang
The double-sided cooling (DSC) module introduces greater thermomechanical stress compared to single-sided cooling (SSC) modules, posing a significant threat to reliability. The manufacturing process is complex, requiring multiple sintering or reflow operations. Due to gravitational factors, this results in uneven thickness in the solder layer, further exacerbating the reliability issues. This article investigates the failure mechanism of the middle solder layer (SAC305) in flip-chip double-sided cooling (FCDSC) modules under thermal cycling conditions using a thermomechanical coupled model. The results indicate that when the solder layer tilt angle reaches 1.53°, the lifetime is reduced by 99.3%. Local viscoplastic strain in the solder at stress concentration areas is identified as a key factor in solder layer fatigue failure. Subsequent experiments confirm that fatigue cracks occur on the thinner side of the solder layer. There, the coarsening of the Ag3Sn eutectic phase is more severe, leading to reduced tensile strength, thus becoming a crack initiation site. Finally, the protrusions-spacer technique is proposed to control the evenness of the solder layer, with experiments demonstrating an average reduction in solder layer tilt by 79.7%.
{"title":"Failure Mechanism and Reliability Research of Solder Layer Tilt in Double-Sided Cooling Power Modules","authors":"Guoliao Sun;Wen Jing;Siyuan Lu;Cheng Peng;Wenhui Zhu;Liancheng Wang","doi":"10.1109/TCPMT.2024.3447124","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3447124","url":null,"abstract":"The double-sided cooling (DSC) module introduces greater thermomechanical stress compared to single-sided cooling (SSC) modules, posing a significant threat to reliability. The manufacturing process is complex, requiring multiple sintering or reflow operations. Due to gravitational factors, this results in uneven thickness in the solder layer, further exacerbating the reliability issues. This article investigates the failure mechanism of the middle solder layer (SAC305) in flip-chip double-sided cooling (FCDSC) modules under thermal cycling conditions using a thermomechanical coupled model. The results indicate that when the solder layer tilt angle reaches 1.53°, the lifetime is reduced by 99.3%. Local viscoplastic strain in the solder at stress concentration areas is identified as a key factor in solder layer fatigue failure. Subsequent experiments confirm that fatigue cracks occur on the thinner side of the solder layer. There, the coarsening of the Ag3Sn eutectic phase is more severe, leading to reduced tensile strength, thus becoming a crack initiation site. Finally, the protrusions-spacer technique is proposed to control the evenness of the solder layer, with experiments demonstrating an average reduction in solder layer tilt by 79.7%.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1585-1592"},"PeriodicalIF":2.3,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142551996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3471051
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Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3471053
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Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3484225
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Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3471055
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information","authors":"","doi":"10.1109/TCPMT.2024.3471055","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3471055","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"C4-C4"},"PeriodicalIF":2.3,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10739377","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142551995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3484223
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Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3484219
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information","authors":"","doi":"10.1109/TCPMT.2024.3484219","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3484219","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 10","pages":"C2-C2"},"PeriodicalIF":2.3,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10739376","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142555069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-18DOI: 10.1109/TCPMT.2024.3462944
Jianyu Feng;Rong Fu;Yunqian Song;Qidong Wang;Chuan Chen;Liqiang Cao
The three-dimensional integration technology is an effective solution of extending Moore’s law, with better performance and higher density. However, the temperature rise caused by hot spots in 3-D integration will be more prominent. By extracting the equivalent thermal conductivity of the microbump layer and the chip with TSVs, the equivalent analytical model for detailed 3-D integration structure is proposed in this article. The accuracy of equivalence is verified using finite element simulation, and the model is used to calculate the thermal resistance and to predict the maximum temperature of the hot spot. In 3-D integration, the second conduction path can significantly reduce the temperature of the hot spot. A new analytical solution is proposed in this article for calculating thermal resistance and predicting the maximum temperature of the hot spot in 3-D integration. The results demonstrate that the thermal resistance network model proposed can precisely predict the temperature rise of the hot spot. For hot spots with different sizes, the error between simulation and network model is merely within $2~^{circ }$