A transient-enhanced output-capacitorless LDO regulator with non-inverting pull–push gain stage

Abstract

A novel non-inverting pull–push gain stage output-capacitorless low-dropout regulator (OCL-LDO) is introduced, designed specifically for power management of system-on-chip (SoC). The incorporation of an innovative non-inverting gain stage (NIGS) serves to shift the non-dominant parasitic poles to higher frequencies, thereby enhancing the overall stability of the system. The proposed pull-push configuration markedly improves the slew rate limitation at the gate of the power transistor. Post-layout simulation outcomes, corroborated through a 180-nm CMOS fabrication process, indicate that the proposed LDO regulator maintains stability across a wide range of loading currents, from 0 mA to 100 mA, with a Miller compensation capacitance of only 3.5 pF. The circuit operates with a quiescent current of 143 μA when powered by a 1.5 V single supply. The LDO regulator boasts a dropout voltage of 300 mV, enabling it to deliver up to 100 mA of load current. Simulation results show that the undershoot voltage is only 63.7 mV when the load current jumps from 0 to 100 mA with edge of 100 ns, while employing a 100 pF capacitance load. The recovery time to return to equilibrium post this abrupt change is approximately 0.15 μs. The proposed OCL-LDO regulator exhibits a substantial enhancement in transient response compared to its predecessors, alongside a harmonized balance between line regulation and load regulation performance parameters.