Key space estimation and security analysis of superlattice physical unclonable function

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics Journal Pub Date : 2024-07-16 DOI:10.1016/j.mejo.2024.106320
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Abstract

The key space, a crucial metric in discerning the strength of PUFs, holds significant importance for their security. However, there is insufficient research on superlattice PUFs. This paper integrates superlattice into the PUF theory framework, exploring its physical mechanisms and properties. The focus is on estimating the key space of superlattice PUFs and conducting a security analysis, encompassing resistance to brute force cracking, birthday attacks, and cloning attacks. The results show that its key space can be up to 24,500×50, with a huge number of Challenge-Response Pairs (CRP) set, belonging to strong PUF. It has significant advantages over conventional PUFs, making it applicable in the domains of cryptography and information security.

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超晶格物理不可克隆函数的密钥空间估计与安全性分析
密钥空间是判别 PUF 强度的关键指标,对其安全性具有重要意义。然而,关于超晶格 PUF 的研究还不够充分。本文将超晶格纳入 PUF 理论框架,探索其物理机制和特性。重点是估算超晶格 PUF 的密钥空间并进行安全性分析,包括对暴力破解、生日攻击和克隆攻击的抵抗。结果表明,它的密钥空间可达 24500×50,具有大量的挑战-响应对(CRP)集,属于强 PUF。与传统的 PUF 相比,它具有明显的优势,适用于密码学和信息安全领域。
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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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