A 18-bit 1-MS/s fully-differential SAR ADC with digital calibration achieving 96.1 dB SNDR

Abstract

This paper presents a 18-bit 1 MS/s fully-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC) achieving an ENOB of 15.7-bit. To achieve higher performance, a differential DAC utilizing both split and monotonic switching timing is designed. For both dynamic and static performance improvement, five techniques are proposed. First, a foreground digital self-calibration method based on normalized-full-scale-referencing is described to eliminate the capacitor mismatch errors. L-segment capacitors are utilized to measure and calculate the bit weights of other capacitors. Second, a DNL enhancement technique is presented. The fractional capacitors are used to subtract an analog voltage from the DAC before the conversion is finished, which further improve the ADC performance. Third, an adaptive-tracking-extra-bit-trail together with comparator noise extraction and correction for further accuracy enhancement is proposed. Forth, a harmonic calibration technique, which can efficiently attenuate 2-order and 3-order harmonic is introduced. Fifth, a comparator with ultra-low noise and offset is designed to meet the 18-bit 1-MS/s ADC. The ADC is fabricated in a 0.18-μm 5-V CMOS process. It measures a 96.1 dB SNDR and a 110.7 dB SFDR. The DNL and INL are within ±0.32 LSB and ±0.5 LSB, respectively. The overall power consumption of ADC core, drawn from the 5 V power supply, is 45 mW.