A 128 × 128 SPAD LiDAR sensor with column-parallel 25 ps resolution TA-ADCs

IF 4.8 4区 物理与天体物理 Q2 PHYSICS, CONDENSED MATTER Journal of Semiconductors Pub Date : 2024-07-31 DOI:10.1088/1674-4926/24030019
Na Tian, Zhe Wang, Kai Ma, Xu Yang, Nan Qi, Jian Liu, Nanjian Wu, Runjiang Dou and Liyuan Liu
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Abstract

This paper presents a design of single photon avalanche diode (SPAD) light detection and ranging (LiDAR) sensor with 128 × 128 pixels and 128 column-parallel time-to-analog-merged-analog-to-digital converts (TA-ADCs). Unlike the conventional TAC-based SPAD LiDAR sensor, in which the TAC and ADC are separately implemented, we propose to merge the TAC and ADC by sharing their capacitors, thus avoiding the analog readout noise of TAC’s output buffer, improving the conversion rate, and reducing chip area. The reverse start-stop logic is employed to reduce the power of the TA-ADC. Fabricated in a 180 nm CMOS process, our prototype sensor exhibits a timing resolution of 25 ps, a DNL of +0.30/−0.77 LSB, an INL of +1.41/−2.20 LSB, and a total power consumption of 190 mW. A flash LiDAR system based on this sensor demonstrates the function of 2D/3D imaging with 128 × 128 resolution, 25 kHz inter-frame rate, and sub-centimeter ranging precision.
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配备列并行 25 ps 分辨率 TA-ADC 的 128 × 128 SPAD 激光雷达传感器
本文介绍了一种单光子雪崩二极管(SPAD)光探测与测距(LiDAR)传感器的设计,该传感器具有 128 × 128 像素和 128 列并行时间-模拟-合并-模拟-数字转换器(TA-ADC)。传统的基于 TAC 的 SPAD 激光雷达传感器中,TAC 和 ADC 是分开实现的,与此不同,我们建议通过共享电容来合并 TAC 和 ADC,从而避免 TAC 输出缓冲器的模拟读出噪声,提高转换率并减少芯片面积。采用反向启停逻辑降低了 TA-ADC 的功耗。我们的传感器原型采用 180 纳米 CMOS 工艺制造,时序分辨率为 25 ps,DNL 为 +0.30/-0.77 LSB,INL 为 +1.41/-2.20 LSB,总功耗为 190 mW。基于该传感器的闪光激光雷达系统展示了 128 × 128 分辨率、25 kHz 帧间速率和亚厘米级测距精度的 2D/3D 成像功能。
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来源期刊
Journal of Semiconductors
Journal of Semiconductors PHYSICS, CONDENSED MATTER-
CiteScore
6.70
自引率
9.80%
发文量
119
期刊介绍: Journal of Semiconductors publishes articles that emphasize semiconductor physics, materials, devices, circuits, and related technology.
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