{"title":"Void Growth and Intermetallic Bridging in Microscale Solder Interconnects Under Thermal Annealing","authors":"Sudarshan Prasanna Prasad;Chetan Jois;Yuvraj Singh;Ganesh Subbarayan;Bharat Penmecha;Prasanna Raghavan","doi":"10.1109/TCPMT.2024.3416430","DOIUrl":null,"url":null,"abstract":"As the pitch and size of microbumps in 2.5-D/ 3-D packages decrease, void evolution in the solder joint volume accompanied by growth of Cu-Sn intermetallic (IMC) phase is a potential reliability concern necessitating further investigation into the underlying mechanisms. In this study, test devices are designed and fabricated to mimic the behavior of fine pitch microbumps of size \n<inline-formula> <tex-math>$30~\\mu $ </tex-math></inline-formula>\nm. These test devices offer the capability of nondestructively observing IMC growth and void evolution. Consequently, they allow continuous observation of phase evolution. These devices also eliminate potential loss of information due to destructive processing techniques. Each fabricated test device consists of multiple Cu-Sn-Cu joints with varying sizes of Sn solder segments that are then aged at \n<inline-formula> <tex-math>$175~ {\\mathrm {^{\\circ}C }}$ </tex-math></inline-formula>\n for a total time of 1000 h, with readouts every 50 or 100 h under scanning electron microscope (SEM). Additionally, trenches are milled in some samples using focused ion beam (FIB) to characterize the various material phases at the Cu-Sn junctions and monitor their growth with thermal aging. The observations from these investigations are reported, and a reaction-diffusion mechanism is proposed to explain the observed Cu-Sn IMC and void evolution due to thermal aging at elevated temperatures.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 7","pages":"1308-1318"},"PeriodicalIF":2.3000,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Components, Packaging and Manufacturing Technology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10562312/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
As the pitch and size of microbumps in 2.5-D/ 3-D packages decrease, void evolution in the solder joint volume accompanied by growth of Cu-Sn intermetallic (IMC) phase is a potential reliability concern necessitating further investigation into the underlying mechanisms. In this study, test devices are designed and fabricated to mimic the behavior of fine pitch microbumps of size
$30~\mu $
m. These test devices offer the capability of nondestructively observing IMC growth and void evolution. Consequently, they allow continuous observation of phase evolution. These devices also eliminate potential loss of information due to destructive processing techniques. Each fabricated test device consists of multiple Cu-Sn-Cu joints with varying sizes of Sn solder segments that are then aged at
$175~ {\mathrm {^{\circ}C }}$
for a total time of 1000 h, with readouts every 50 or 100 h under scanning electron microscope (SEM). Additionally, trenches are milled in some samples using focused ion beam (FIB) to characterize the various material phases at the Cu-Sn junctions and monitor their growth with thermal aging. The observations from these investigations are reported, and a reaction-diffusion mechanism is proposed to explain the observed Cu-Sn IMC and void evolution due to thermal aging at elevated temperatures.
期刊介绍:
IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.